Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ROCKCHIP HDMI PHY WITH INNO IP BLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  - compatible : "rockchip,rk3228-hdmi-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 		"rockchip,rk3328-hdmi-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  - reg : the address offset of register for hdmi phy configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  - #phy-cells : must be 0. See ./phy-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  - clocks and clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	- the "sysclk" clock is required by the phy module, used to system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	  control and register configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	- the "refclk" clock is reference crystal oscillator clock input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	  to PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  - #clock-cells: should be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  - clock-output-names : shall be the corresponding names of the outputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  - rockchip,phy-table: the parameter table of hdmi phy configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	hdmi_phy: hdmi-phy@12030000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		compatible = "rockchip,rk3228-hdmi-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		reg = <0x12030000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		clock-names = "sysclk", "refclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		clock-output-names = "hdmiphy_phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		rockchip,phy-table =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 			<165000000 0x07 0x0a 0x0a 0x0a 0x00 0x00 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 				   0x08 0x08 0x00 0xac 0xcc 0xcc 0xcc>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 			<340000000 0x0b 0x0d 0x0d 0x0d 0x07 0x15 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 				   0x08 0x08 0x3f 0xac 0xcc 0xcd 0xdd>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			<594000000 0x10 0x1a 0x1a 0x1a 0x07 0x15 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 				   0x08 0x08 0x00 0xac 0xcc 0xcc 0xcc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Then the PHY can be used in other nodes such as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	hdmi: hdmi@200a0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		compatible = "rockchip,rk3228-dw-hdmi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		phys = <&hdmi_phy>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		phy-names = "hdmi_phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	};