Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Microsemi Ocelot SerDes muxing driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) -------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) On Microsemi Ocelot, there is a handful of registers in HSIO address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) space for setting up the SerDes to switch port muxing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) A SerDes X can be "muxed" to work with switch port Y or Z for example.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) One specific SerDes can also be used as a PCIe interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Also, SERDES6G number (aka "macro") 0 is the only interface supporting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) QSGMII.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) This is a child of the HSIO syscon ("mscc,ocelot-hsio", see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Documentation/devicetree/bindings/mips/mscc.txt) on the Microsemi Ocelot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - compatible: should be "mscc,vsc7514-serdes"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - #phy-cells : from the generic phy bindings, must be 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	       The first number defines the input port to use for a given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	       SerDes macro. The second defines the macro to use. They are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	       defined in dt-bindings/phy/phy-ocelot-serdes.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	serdes: serdes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		compatible = "mscc,vsc7514-serdes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		#phy-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	ethernet {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		port1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			phy-handle = <&phy_foo>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			/* Link SERDES1G_5 to port1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			phys = <&serdes 1 SERDES1G_5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	};