^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) MVEBU comphy drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) COMPHY controllers can be found on the following Marvell MVEBU SoCs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Armada 7k/8k (on the CP110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Armada 3700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) It provides a number of shared PHYs used by various interfaces (network, SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) USB, PCIe...).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - compatible: should be one of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * "marvell,comphy-cp110" for Armada 7k/8k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * "marvell,comphy-a3700" for Armada 3700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - reg: should contain the COMPHY register(s) location(s) and length(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 1 entry for Armada 7k/8k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 4 entries for Armada 3700 along with the corresponding reg-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) properties, memory areas are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Generic COMPHY registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Lane 1 (PCIe/GbE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Lane 0 (USB3/GbE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Lane 2 (SATA/USB3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - marvell,system-controller: should contain a phandle to the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) controller node (only for Armada 7k/8k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - #address-cells: should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - #size-cells: should be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Optional properlties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - clocks: pointers to the reference clocks for this device (CP110 only),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) consequently: MG clock, MG Core clock, AXI clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - clock-names: names of used clocks for CP110 only, must be :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) "mg_clk", "mg_core_clk" and "axi_clk".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) A sub-node is required for each comphy lane provided by the comphy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Required properties (child nodes):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - reg: COMPHY lane number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - #phy-cells : from the generic PHY bindings, must be 1. Defines the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) input port to use for a given comphy lane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) cpm_comphy: phy@120000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) compatible = "marvell,comphy-cp110";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) reg = <0x120000 0x6000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) marvell,system-controller = <&cpm_syscon0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) <&CP110_LABEL(clk) 1 18>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) clock-names = "mg_clk", "mg_core_clk", "axi_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) cpm_comphy0: phy@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) cpm_comphy1: phy@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) comphy: phy@18300 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) compatible = "marvell,comphy-a3700";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) reg = <0x18300 0x300>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) <0x1F000 0x400>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) <0x5C000 0x400>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) <0xe0178 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) reg-names = "comphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "lane1_pcie_gbe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "lane0_usb3_gbe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "lane2_sata_usb3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) comphy0: phy@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) comphy1: phy@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) comphy2: phy@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) reg = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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