^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) MediaTek XS-PHY binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) --------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) The XS-PHY controller supports physical layer functionality for USB3.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) GEN2 controller on MediaTek SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Required properties (controller (parent) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) soc-model is the name of SoC, such as mt3611 etc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) when using "mediatek,xsphy" compatible string, you need SoC specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) ones in addition, one of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - "mediatek,mt3611-xsphy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - #address-cells, #size-cells : should use the same values as the root node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - ranges: must be present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Optional properties (controller (parent) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - reg : offset and length of register shared by multiple U3 ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) exclude port's private register, if only U2 ports provided,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) shouldn't use the property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) calibrate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - mediatek,src-coef : u32, coefficient for slew rate calibrate, depends on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) SoC process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Required nodes : a sub-node is required for each port the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) provides. Address range information including the usual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 'reg' property is used inside these nodes to describe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) the controller's topology.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Required properties (port (child) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - reg : address and length of the register set for the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - clocks : a list of phandle + clock-specifier pairs, one for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) entry in clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - clock-names : must contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "ref": 48M reference clock for HighSpeed analog phy; and 26M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) reference clock for SuperSpeedPlus analog phy, sometimes is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 24M, 25M or 27M, depended on platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - #phy-cells : should be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) cell after port phandle is phy type from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - PHY_TYPE_USB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - PHY_TYPE_USB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) The following optional properties are only for debug or HQA test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Optional properties (PHY_TYPE_USB2 port (child) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - mediatek,eye-src : u32, the value of slew rate calibrate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - mediatek,eye-vrt : u32, the selection of VRT reference voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - mediatek,efuse-intr : u32, the selection of Internal Resistor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Optional properties (PHY_TYPE_USB3 port (child) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - mediatek,efuse-intr : u32, the selection of Internal Resistor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - mediatek,efuse-tx-imp : u32, the selection of TX Impedance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - mediatek,efuse-rx-imp : u32, the selection of RX Impedance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) Banks layout of xsphy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) -------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) port offset bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u2 port0 0x0000 MISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 0x0100 FMREG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 0x0300 U2PHY_COM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u2 port1 0x1000 MISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 0x1100 FMREG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 0x1300 U2PHY_COM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u2 port2 0x2000 MISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u31 common 0x3000 DIG_GLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 0x3100 PHYA_GLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u31 port0 0x3400 DIG_LN_TOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0x3500 DIG_LN_TX0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0x3600 DIG_LN_RX0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0x3700 DIG_LN_DAIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 0x3800 PHYA_LN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u31 port1 0x3a00 DIG_LN_TOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 0x3b00 DIG_LN_TX0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 0x3c00 DIG_LN_RX0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 0x3d00 DIG_LN_DAIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 0x3e00 PHYA_LN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DIG_GLB & PHYA_GLB are shared by U31 ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u3phy: usb-phy@11c40000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) reg = <0 0x11c43000 0 0x0200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mediatek,src-ref-clk-mhz = <26>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mediatek,src-coef = <17>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u2port0: usb-phy@11c40000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) reg = <0 0x11c40000 0 0x0400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) clocks = <&clk48m>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) clock-names = "ref";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mediatek,eye-src = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u3port0: usb-phy@11c43000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) reg = <0 0x11c43400 0 0x0500>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clocks = <&clk26m>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clock-names = "ref";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mediatek,efuse-intr = <28>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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