Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) MediaTek Universal Flash Storage (UFS) M-PHY binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) --------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Each UFS M-PHY node should have its own node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) To bind UFS M-PHY with UFS host controller, the controller node should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) contain a phandle reference to UFS M-PHY node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Required properties for UFS M-PHY nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - compatible         : Compatible list, contains the following controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)                        "mediatek,mt8183-ufsphy" for ufs phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)                        persent on MT81xx chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - reg                : Address and length of the UFS M-PHY register set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - #phy-cells         : This property shall be set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - clocks             : List of phandle and clock specifier pairs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clock-names        : List of clock input name strings sorted in the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)                        order as the clocks property. Following clocks are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)                        mandatory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)                        "unipro": Unipro core control clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)                        "mp": M-PHY core control clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	ufsphy: phy@11fa0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		compatible = "mediatek,mt8183-ufsphy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		reg = <0 0x11fa0000 0 0xc000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		clocks = <&infracfg_ao INFRACFG_AO_UNIPRO_SCK_CG>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 			 <&infracfg_ao INFRACFG_AO_UFS_MP_SAP_BCLK_CG>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		clock-names = "unipro", "mp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	ufshci@11270000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		phys = <&ufsphy>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	};