^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) MediaTek T-PHY binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) --------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) T-phy controller supports physical layer functionality for a number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Required properties (controller (parent) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - compatible : should be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "mediatek,generic-tphy-v1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) "mediatek,generic-tphy-v2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) "mediatek,mt2701-u3phy" (deprecated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "mediatek,mt2712-u3phy" (deprecated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "mediatek,mt8173-u3phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) make use of "mediatek,generic-tphy-v1" on mt2701 instead and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "mediatek,generic-tphy-v2" on mt2712 instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - #address-cells: the number of cells used to represent physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) base addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - #size-cells: the number of cells used to represent the size of an address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - ranges: the address mapping relationship to the parent, defined with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - empty value: if optional 'reg' is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - non-empty value: if optional 'reg' is not used. should set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) the child's base address to 0, the physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) within parent's address space, and the length of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) the address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Required nodes : a sub-node is required for each port the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) provides. Address range information including the usual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 'reg' property is used inside these nodes to describe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) the controller's topology.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Optional properties (controller (parent) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - reg : offset and length of register shared by multiple ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) exclude port's private register. It is needed on mt2701
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) and mt8173, but not on mt2712.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) calibrate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - mediatek,src-coef : coefficient for slew rate calibrate, depends on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SoC process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Required properties (port (child) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - reg : address and length of the register set for the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - #phy-cells : should be 1 (See second example)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) cell after port phandle is phy type from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - PHY_TYPE_USB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - PHY_TYPE_USB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - PHY_TYPE_PCIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - PHY_TYPE_SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Optional properties (PHY_TYPE_USB2 port (child) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) - clocks : a list of phandle + clock-specifier pairs, one for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) entry in clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - clock-names : may contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "ref": 48M reference clock for HighSpeed (digital) phy; and 26M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) reference clock for SuperSpeed (digital) phy, sometimes is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 24M, 25M or 27M, depended on platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "da_ref": the reference clock of analog phy, used if the clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) of analog and digital phys are separated, otherwise uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "ref" clock only if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - mediatek,eye-src : u32, the value of slew rate calibrate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - mediatek,eye-vrt : u32, the selection of VRT reference voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) - mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) - mediatek,bc12 : bool, enable BC12 of u2phy if support it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) - mediatek,discth : u32, the selection of disconnect threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) - mediatek,intr : u32, the selection of internal R (resistance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u3phy: usb-phy@11290000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) compatible = "mediatek,mt8173-u3phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) reg = <0 0x11290000 0 0x800>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u2port0: usb-phy@11290800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) reg = <0 0x11290800 0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) clock-names = "ref";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u3port0: usb-phy@11290900 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) reg = <0 0x11290800 0 0x700>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) clocks = <&clk26m>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) clock-names = "ref";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u2port1: usb-phy@11291000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) reg = <0 0x11291000 0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clock-names = "ref";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) Specifying phy control of devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ---------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) Device nodes should specify the configuration required in their "phys"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) property, containing a phandle to the phy port node and a device type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) phy-names for each port are optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #include <dt-bindings/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) usb30: usb@11270000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) phy-names = "usb2-0", "usb3-0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) Layout differences of banks between mt8173/mt2701 and mt2712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) -------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mt8173 and mt2701:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) port offset bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) shared 0x0000 SPLLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 0x0100 FMREG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u2 port0 0x0800 U2PHY_COM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u3 port0 0x0900 U3PHYD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0x0a00 U3PHYD_BANK2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 0x0b00 U3PHYA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 0x0c00 U3PHYA_DA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u2 port1 0x1000 U2PHY_COM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u3 port1 0x1100 U3PHYD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 0x1200 U3PHYD_BANK2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 0x1300 U3PHYA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 0x1400 U3PHYA_DA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u2 port2 0x1800 U2PHY_COM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mt2712:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) port offset bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u2 port0 0x0000 MISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 0x0100 FMREG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 0x0300 U2PHY_COM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u3 port0 0x0700 SPLLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0x0800 CHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 0x0900 U3PHYD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 0x0a00 U3PHYD_BANK2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 0x0b00 U3PHYA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 0x0c00 U3PHYA_DA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u2 port1 0x1000 MISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 0x1100 FMREG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 0x1300 U2PHY_COM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u3 port1 0x1700 SPLLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 0x1800 CHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 0x1900 U3PHYD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 0x1a00 U3PHYD_BANK2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 0x1b00 U3PHYA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 0x1c00 U3PHYA_DA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u2 port2 0x2000 MISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SPLLC shared by u3 ports and FMREG shared by u2 ports on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) mt8173/mt2701 are put back into each port; a new bank MISC for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u2 ports and CHIP for u3 ports are added on mt2712.
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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