Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) STMicroelectronics STi MIPHY365x PHY binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) ============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) This binding describes a miphy device that is used to control PHY hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) for SATA and PCIe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties (controller (parent) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible    : Should be "st,miphy365x-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 		  containing the miphy registers and integer array should contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 		  an entry for each port sub-node, specifying the control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 		  register offset inside the sysconfig group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Required nodes	:  A sub-node is required for each channel the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		   provides. Address range information including the usual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		   'reg' and 'reg-names' properties are used inside these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		   nodes to describe the controller's topology. These nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		   are translated by the driver's .xlate() function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Required properties (port (child) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - #phy-cells 	: Should be 1 (See second example)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		  Cell after port phandle is device type from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 			- PHY_TYPE_SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			- PHY_TYPE_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - reg        	: Address and length of register sets for each device in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		  "reg-names"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - reg-names     : The names of the register addresses corresponding to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		  registers filled in "reg":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 			- sata:   For SATA devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 			- pcie:   For PCIe devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Optional properties (port (child) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - st,sata-gen	     :	Generation of locally attached SATA IP. Expected values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			are {1,2,3). If not supplied generation 1 hardware will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 			be expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - st,pcie-tx-pol-inv :	Bool property to invert the polarity PCIe Tx (Txn/Txp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - st,sata-tx-pol-inv :	Bool property to invert the polarity SATA Tx (Txn/Txp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	miphy365x_phy: miphy365x@fe382000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		compatible      = "st,miphy365x-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		st,syscfg  	= <&syscfg_rear 0x824 0x828>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		#address-cells	= <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		#size-cells	= <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		phy_port0: port@fe382000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			reg-names = "sata", "pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			#phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			st,sata-gen = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		phy_port1: port@fe38a000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 			reg-names = "sata", "pcie", "syscfg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			#phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 			st,pcie-tx-pol-inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) Specifying phy control of devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) =================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Device nodes should specify the configuration required in their "phys"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) property, containing a phandle to the phy port node and a device type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <dt-bindings/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	sata0: sata@fe380000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 		phys	  = <&phy_port0 PHY_TYPE_SATA>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	};