^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) STMicroelectronics STi MIPHY28LP PHY binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) This binding describes a miphy device that is used to control PHY hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) for SATA, PCIe or USB3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Required properties (controller (parent) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - compatible : Should be "st,miphy28lp-phy".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - st,syscfg : Should be a phandle of the system configuration register group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) which contain the SATA, PCIe or USB3 mode setting bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Required nodes : A sub-node is required for each channel the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) provides. Address range information including the usual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 'reg' and 'reg-names' properties are used inside these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) nodes to describe the controller's topology. These nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) are translated by the driver's .xlate() function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Required properties (port (child) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - #phy-cells : Should be 1 (See second example)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Cell after port phandle is device type from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - PHY_TYPE_SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - PHY_TYPE_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - PHY_TYPE_USB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - reg : Address and length of the register set for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - reg-names : The names of the register addresses corresponding to the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) filled in "reg". It can also contain the offset of the system configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) registers used as glue-logic to setup the device for SATA/PCIe or USB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - st,syscfg : Offset of the parent configuration register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - resets : phandle to the parent reset controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - reset-names : Associated name must be "miphy-sw-rst".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Optional properties (port (child) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - st,osc-rdy : to check the MIPHY0_OSC_RDY status in the glue-logic. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) is not available in all the MiPHY. For example, for STiH407, only the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MiPHY0 has this bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - st,osc-force-ext : to select the external oscillator. This can change from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) different MiPHY inside the same SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - st,sata_gen : to select which SATA_SPDMODE has to be set in the SATA system config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) line).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - st,scc-on : enable ssc to reduce effects of EMI (only for sata or PCIe).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - st,tx-impedance-comp : to compensate tx impedance avoiding out of range values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) miphy28lp_phy: miphy28lp@9b22000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) compatible = "st,miphy28lp-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) st,syscfg = <&syscfg_core>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) phy_port0: port@9b22000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) reg = <0x9b22000 0xff>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) <0x9b09000 0xff>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) <0x9b04000 0xff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) reg-names = "sata-up",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "pcie-up",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "pipew";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) st,syscfg = <0x114 0x818 0xe0 0xec>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) st,osc-rdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) reset-names = "miphy-sw-rst";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) phy_port1: port@9b2a000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) reg = <0x9b2a000 0xff>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) <0x9b19000 0xff>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) <0x9b14000 0xff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) reg-names = "sata-up",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "pcie-up",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "pipew";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) st,syscfg = <0x118 0x81c 0xe4 0xf0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) st,osc-force-ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) reset-names = "miphy-sw-rst";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) phy_port2: port@8f95000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) reg = <0x8f95000 0xff>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) <0x8f90000 0xff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) reg-names = "pipew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "usb3-up";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) st,syscfg = <0x11c 0x820>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) reset-names = "miphy-sw-rst";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) Specifying phy control of devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) =================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) Device nodes should specify the configuration required in their "phys"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) property, containing a phandle to the miphy device node and an index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) specifying which configuration to use, as described in phy-bindings.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) sata0: sata@9b20000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) phys = <&phy_port0 PHY_TYPE_SATA>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) Macro definitions for the supported miphy configuration can be found in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) include/dt-bindings/phy/phy.h
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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