Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) ===========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) This binding describes the USB PHY hardware provided by the RCU module on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Lantiq XWAY SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) This node has to be a sub node of the Lantiq RCU block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) -------------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Required properties (controller (parent) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - compatible	: Should be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 			"lantiq,ase-usb2-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 			"lantiq,danube-usb2-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 			"lantiq,xrx100-usb2-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 			"lantiq,xrx200-usb2-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 			"lantiq,xrx300-usb2-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - reg		: Defines the following sets of registers in the parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		  syscon device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 			- Offset of the USB PHY configuration register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 			- Offset of the USB Analog configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 			  register (only for xrx200 and xrx200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - clocks	: References to the (PMU) "phy" clk gate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - clock-names	: Must be "phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - resets	: References to the RCU USB configuration reset bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - reset-names	: Must be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 			"phy" (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 			"ctrl" (shared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) -------------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Example for the USB PHYs on an xRX200 SoC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	usb_phy0: usb2-phy@18 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		compatible = "lantiq,xrx200-usb2-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		reg = <0x18 4>, <0x38 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		clocks = <&pmu PMU_GATE_USB0_PHY>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		clock-names = "phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		resets = <&reset1 4 4>, <&reset0 4 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		reset-names = "phy", "ctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	};