Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Device tree bindings for HiSilicon INNO USB2 PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: Should be one of the following strings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	"hisilicon,inno-usb2-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	"hisilicon,hi3798cv200-usb2-phy".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - reg: Should be the address space for PHY configuration register in peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)   controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   reference clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - #address-cells: Must be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - #size-cells: Must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) The INNO USB2 PHY device should be a child node of peripheral controller that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) contains the PHY configuration register, and each device suppports up to 2 PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ports which are represented as child nodes of INNO USB2 PHY device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Required properties for PHY port node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - reg: The PHY port instance number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - #phy-cells: Defined by generic PHY bindings.  Must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - resets: The phandle and reset specifier pair for PHY port reset signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Refer to phy/phy-bindings.txt for the generic PHY binding properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) perictrl: peripheral-controller@8a20000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	reg = <0x8a20000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	ranges = <0x0 0x8a20000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	usb2_phy1: usb2-phy@120 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		compatible = "hisilicon,hi3798cv200-usb2-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		reg = <0x120 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		resets = <&crg 0xbc 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		usb2_phy1_port0: phy@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			resets = <&crg 0xbc 8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		usb2_phy1_port1: phy@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			resets = <&crg 0xbc 9>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	usb2_phy2: usb2-phy@124 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		compatible = "hisilicon,hi3798cv200-usb2-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		reg = <0x124 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		resets = <&crg 0xbc 6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		usb2_phy2_port0: phy@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 			reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 			#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 			resets = <&crg 0xbc 10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };