Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) HiSilicon STB PCIE/SATA/USB3 PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: Should be "hisilicon,hi3798cv200-combphy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: Should be the address space for COMBPHY configuration and state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)   registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   PERI_COMBPHY0_STATE for COMBPHY0 Hi3798CV200 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - #phy-cells: Should be 1.  The cell number is used to select the phy mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   as defined in <dt-bindings/phy/phy.h>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clocks: The phandle to clock provider and clock specifier pair.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - resets: The phandle to reset controller and reset specifier pair.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Refer to phy/phy-bindings.txt for the generic PHY binding properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - hisilicon,fixed-mode: If the phy device doesn't support mode select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   but a fixed mode setting, the property should be present to specify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   the particular mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - hisilicon,mode-select-bits: If the phy device support mode select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   this property should be present to specify the register bits in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   peripheral controller, as a 3 integers tuple:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)   <register_offset bit_shift bit_mask>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - Between hisilicon,fixed-mode and hisilicon,mode-select-bits, one and only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   one of them should be present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - The device node should be a child of peripheral controller that contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)   COMBPHY configuration/state and PERI_CTRL register used to select PHY mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   Refer to arm/hisilicon/hisilicon.txt for the parent peripheral controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) perictrl: peripheral-controller@8a20000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		     "simple-mfd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	reg = <0x8a20000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	ranges = <0x0 0x8a20000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	combphy0: phy@850 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		compatible = "hisilicon,hi3798cv200-combphy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		reg = <0x850 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		#phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		clocks = <&crg HISTB_COMBPHY0_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		resets = <&crg 0x188 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		hisilicon,fixed-mode = <PHY_TYPE_USB3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	combphy1: phy@858 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		compatible = "hisilicon,hi3798cv200-combphy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		reg = <0x858 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		#phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		clocks = <&crg HISTB_COMBPHY1_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		resets = <&crg 0x188 12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };