^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Cadence Sierra PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) -----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - resets: Must contain an entry for each in reset-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) See ../reset/reset.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - reset-names: Must include "sierra_reset" and "sierra_apb".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) "sierra_reset" must control the reset line to the PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) "sierra_apb" must control the reset line to the APB PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) interface ("sierra_apb" is optional).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - reg: register range for the PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - #address-cells: Must be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - #size-cells: Must be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - clocks: Must contain an entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) See ../clocks/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - clock-names: Must contain "cmn_refclk_dig_div" and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) "cmn_refclk1_dig_div" for configuring the frequency of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) the clock to the lanes. "phy_clk" is deprecated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - cdns,autoconf: A boolean property whose presence indicates that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PHY registers will be configured by hardware. If not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) present, all sub-node optional properties must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) provided.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Sub-nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Each group of PHY lanes with a single master lane should be represented as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) a sub-node. Note that the actual configuration of each lane is determined by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) hardware strapping, and must match the configuration specified here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Sub-node required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - #phy-cells: Generic PHY binding; must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - reg: The master lane number. This is the lowest numbered lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) in the lane group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - resets: Must contain one entry which controls the reset line for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) master lane of the sub-node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) See ../reset/reset.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Sub-node optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - cdns,num-lanes: Number of lanes in this group. From 1 to 4. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) group is made up of consecutive lanes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - cdns,phy-type: Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) configuration of lanes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) pcie_phy4: pcie-phy@fd240000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) compatible = "cdns,sierra-phy-t0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) reg = <0x0 0xfd240000 0x0 0x40000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) resets = <&phyrst 0>, <&phyrst 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) reset-names = "sierra_reset", "sierra_apb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) clocks = <&phyclock>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) clock-names = "phy_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pcie0_phy0: pcie-phy@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) resets = <&phyrst 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) cdns,num-lanes = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) cdns,phy-type = <PHY_TYPE_PCIE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pcie0_phy1: pcie-phy@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) reg = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) resets = <&phyrst 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) cdns,num-lanes = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) cdns,phy-type = <PHY_TYPE_PCIE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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