Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) $id: http://devicetree.org/schemas/phy/calxeda-combophy.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) title: Calxeda Highbank Combination PHYs binding for SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   The Calxeda Combination PHYs connect the SoC to the internal fabric
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   and to SATA connectors. The PHYs support multiple protocols (SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   SGMII, PCIe) and can be assigned to different devices (SATA or XGMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   controller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   Programming the PHYs is typically handled by those device drivers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   not by a dedicated PHY driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   - Andre Przywara <andre.przywara@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)     const: calxeda,hb-combophy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   '#phy-cells':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)     const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   phydev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)     description: device ID for programming the ComboPHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)     $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)     maximum: 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)   - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)   - phydev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)   - '#phy-cells'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)     combophy5: combo-phy@fff5d000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)                    compatible = "calxeda,hb-combophy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)                    #phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)                    reg = <0xfff5d000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)                    phydev = <31>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)                };