Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Xilinx AXI PCIe Root Port Bridge DT description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - #address-cells: Address representation for root ports, set to <3>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - #size-cells: Size representation for root ports, set to <2>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - #interrupt-cells: specifies the number of cells needed to encode an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	interrupt source. The value must be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg: Should contain AXI PCIe registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - device_type: must be "pci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - interrupts: Should contain AXI PCIe interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - interrupt-map-mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   interrupt-map: standard PCI properties to define the mapping of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	PCI interface to interrupt numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - ranges: ranges for the PCI memory regions (I/O space region is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	supported by hardware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	Please refer to the standard PCI bus binding document for a more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	detailed explanation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Optional properties for Zynq/Microblaze:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - bus-range: PCI bus numbers covered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Interrupt controller child node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) +++++++++++++++++++++++++++++++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - interrupt-controller: identifies the node as an interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - #address-cells: specifies the number of cells needed to encode an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	address. The value must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - #interrupt-cells: specifies the number of cells needed to encode an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	interrupt source. The value must be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) NOTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) The core provides a single interrupt for both INTx/MSI messages. So,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) created a interrupt controller node to support 'interrupt-map' DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) functionality.  The driver will create an IRQ domain for this map, decode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) the four INTx interrupts in ISR and route them to this domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ++++++++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Zynq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	pci_express: axi-pcie@50000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		#address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		compatible = "xlnx,axi-pcie-host-1.00.a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		reg = < 0x50000000 0x1000000 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		interrupts = < 0 52 4 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		interrupt-map-mask = <0 0 0 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		interrupt-map = <0 0 0 1 &pcie_intc 1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 				<0 0 0 2 &pcie_intc 2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 				<0 0 0 3 &pcie_intc 3>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 				<0 0 0 4 &pcie_intc 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		pcie_intc: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 			#address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) Microblaze:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	pci_express: axi-pcie@10000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		#address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		compatible = "xlnx,axi-pcie-host-1.00.a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 		reg = <0x10000000 0x4000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 		device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		interrupt-parent = <&microblaze_0_intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 		interrupts = <1 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 		interrupt-map-mask = <0 0 0 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 		interrupt-map = <0 0 0 1 &pcie_intc 1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 				<0 0 0 2 &pcie_intc 2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 				<0 0 0 3 &pcie_intc 3>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 				<0 0 0 4 &pcie_intc 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 		ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 		pcie_intc: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 			interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 			#address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 			#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	};