Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Xilinx NWL PCIe Root Port Bridge DT description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: Should contain "xlnx,nwl-pcie-2.11"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - #address-cells: Address representation for root ports, set to <3>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - #size-cells: Size representation for root ports, set to <2>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - #interrupt-cells: specifies the number of cells needed to encode an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	interrupt source. The value must be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg: Should contain Bridge, PCIe Controller registers location,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	configuration space, and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - reg-names: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	"breg": bridge registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	"pcireg": PCIe controller registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	"cfg": configuration space region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - device_type: must be "pci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - interrupts: Should contain NWL PCIe interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - interrupt-names: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	"msi1, msi0": interrupt asserted when an MSI is received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	"intx": interrupt asserted when a legacy interrupt is received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	"misc": interrupt asserted when miscellaneous interrupt is received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - interrupt-map-mask and interrupt-map: standard PCI properties to define the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	mapping of the PCI interface to interrupt numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - ranges: ranges for the PCI memory regions (I/O space region is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	supported by hardware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	Please refer to the standard PCI bus binding document for a more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	detailed explanation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - msi-controller: indicates that this is MSI controller node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - msi-parent:  MSI parent of the root complex itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - legacy-interrupt-controller: Interrupt controller device node for Legacy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	- interrupt-controller: identifies the node as an interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	- #interrupt-cells: should be set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	- #address-cells: specifies the number of cells needed to encode an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		address. The value must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ++++++++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) nwl_pcie: pcie@fd0e0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	#address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	compatible = "xlnx,nwl-pcie-2.11";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	msi-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	interrupt-parent = <&gic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	interrupt-names = "msi0", "msi1", "intx", "dummy", "misc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	msi-parent = <&nwl_pcie>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	reg = <0x0 0xfd0e0000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	      <0x0 0xfd480000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	      <0x80 0x00000000 0x0 0x1000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	reg-names = "breg", "pcireg", "cfg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		  0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	pcie_intc: legacy-interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		#address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };