Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * AppliedMicro X-Gene v1 PCIe MSI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - compatible: should be "apm,xgene1-msi" to identify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	      X-Gene v1 PCIe MSI controller block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reg: physical base address (0x79000000) and length (0x900000) for controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)        registers. These registers include the MSI termination address and data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)        registers as well as the MSI interrupt status registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - reg-names: not required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - interrupts: A list of 16 interrupt outputs of the controller, starting from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	      interrupt number 0x10 to 0x1f.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - interrupt-names: not required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Each PCIe node needs to have property msi-parent that points to an MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) controller node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) SoC DTSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	+ MSI node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	msi@79000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		compatible = "apm,xgene1-msi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		msi-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		reg = <0x00 0x79000000 0x0 0x900000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		interrupts = 	<0x0 0x10 0x4>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 				<0x0 0x11 0x4>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 				<0x0 0x12 0x4>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 				<0x0 0x13 0x4>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 				<0x0 0x14 0x4>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 				<0x0 0x15 0x4>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 				<0x0 0x16 0x4>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 				<0x0 0x17 0x4>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 				<0x0 0x18 0x4>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 				<0x0 0x19 0x4>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 				<0x0 0x1a 0x4>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 				<0x0 0x1b 0x4>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 				<0x0 0x1c 0x4>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 				<0x0 0x1d 0x4>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 				<0x0 0x1e 0x4>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 				<0x0 0x1f 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	+ PCIe controller node with msi-parent property pointing to MSI node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	pcie0: pcie@1f2b0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		#address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		reg-names = "csr", "cfg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 			  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 			      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		interrupt-map-mask = <0x0 0x0 0x0 0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 				 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 				 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 				 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		clocks = <&pcie0clk 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		msi-parent= <&msi>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	};