^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Socionext UniPhier PCIe host controller bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This describes the devicetree bindings for PCIe host controller implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) on Socionext UniPhier SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) It shares common functions with the PCIe DesignWare core driver and inherits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) common properties defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Documentation/devicetree/bindings/pci/designware-pcie.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - compatible: Should be "socionext,uniphier-pcie".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - reg: Specifies offset and length of the register set for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) According to the reg-names, appropriate register sets are required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - reg-names: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "dbi" - controller configuration registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "link" - SoC-specific glue layer registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) "config" - PCIe configuration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) "atu" - iATU registers for DWC version 4.80 or later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - clocks: A phandle to the clock gate for PCIe glue layer including
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) the host controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - resets: A phandle to the reset line for PCIe glue layer including
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) the host controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - interrupts: A list of interrupt specifiers. According to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) interrupt-names, appropriate interrupts are required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - interrupt-names: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) "dma" - DMA interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) "msi" - MSI interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - phys: A phandle to generic PCIe PHY. According to the phy-names, appropriate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) phys are required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - phy-names: Must be "pcie-phy".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Required sub-node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - legacy-interrupt-controller: Specifies interrupt controller for legacy PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Required properties for legacy-interrupt-controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - interrupt-controller: identifies the node as an interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - #interrupt-cells: specifies the number of cells needed to encode an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) interrupt source. The value must be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - interrupt-parent: Phandle to the parent interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - interrupts: An interrupt specifier for legacy interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) pcie: pcie@66000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) reg-names = "dbi", "link", "config";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) <0x2fff0000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) clocks = <&sys_clk 24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) resets = <&sys_rst 24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) num-lanes = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) num-viewport = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) bus-range = <0x0 0xff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ranges =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* downstream I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* non-prefetchable memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) interrupt-names = "dma", "msi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) interrupts = <0 224 4>, <0 225 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) interrupt-map-mask = <0 0 0 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) <0 0 0 2 &pcie_intc 1>, /* INTB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) <0 0 0 3 &pcie_intc 2>, /* INTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) <0 0 0 4 &pcie_intc 3>; /* INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pcie_intc: legacy-interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) interrupt-parent = <&gic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) interrupts = <0 226 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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