^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) TI PCI Controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) PCIe DesignWare Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Should be "ti,dra7-pcie-ep" for EP (deprecated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Should be "ti,dra726-pcie-rc" for dra72x in RC mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Should be "ti,dra726-pcie-ep" for dra72x in EP mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - phys : list of PHY specifiers (used by generic PHY framework)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) number of PHYs as specified in *phys* property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) where <X> is the instance number of the pcie from the HW spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - num-lanes as specified in ../designware-pcie.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) module and the register offset to specify lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) selection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) HOST MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) =========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - reg : Two register ranges as listed in the reg-names property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - reg-names : The first entry must be "ti-conf" for the TI-specific registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) The second entry must be "rc-dbics" for the DesignWare PCIe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) The third entry must be "config" for the PCIe configuration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - interrupts : Two interrupt entries must be specified. The first one is for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) main interrupt line and the second for MSI interrupt line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - #address-cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #size-cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #interrupt-cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) device_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) interrupt-map-mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) interrupt-map : as specified in ../designware-pcie.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) should contain the register offset within syscon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) and the 2nd argument should contain the bit field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) for setting the bit to enable unaligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DEVICE MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ===========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - reg : Four register ranges as listed in the reg-names property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - reg-names : "ti-conf" for the TI-specific registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "ep_dbics" for the standard configuration registers as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) they are locally accessed within the DIF CS space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "ep_dbics2" for the standard configuration registers as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) they are locally accessed within the DIF CS2 space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "addr_space" used to map remote RC address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) - interrupts : one interrupt entries must be specified for main interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - num-ib-windows : number of inbound address translation windows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - num-ob-windows : number of outbound address translation windows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) should contain the register offset within syscon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) and the 2nd argument should contain the bit field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) for setting the bit to enable unaligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) Optional Property:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - gpios : Should be added if a GPIO line is required to drive PERST# line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) NOTE: Two DT nodes may be added for each PCI controller; one for host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mode and another for device mode. So in order for PCI to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) work in host mode, EP mode DT node should be disabled and in order to PCI to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) work in EP mode, host mode DT node should be disabled. Host mode and EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mode are mutually exclusive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) axi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ranges = <0x51000000 0x51000000 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 0x0 0x20000000 0x10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pcie@51000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) compatible = "ti,dra7-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) reg-names = "rc_dbics", "ti_conf", "config";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) interrupts = <0 232 0x4>, <0 233 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ranges = <0x81000000 0 0 0x03000 0 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) num-lanes = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ti,hwmods = "pcie1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) phys = <&pcie1_phy>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) phy-names = "pcie-phy0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) interrupt-map-mask = <0 0 0 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) interrupt-map = <0 0 0 1 &pcie_intc 1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) <0 0 0 2 &pcie_intc 2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) <0 0 0 3 &pcie_intc 3>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) <0 0 0 4 &pcie_intc 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pcie_intc: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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