^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Rockchip AXI PCIe Root Port Bridge DT description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - #address-cells: Address representation for root ports, set to <3>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - #size-cells: Size representation for root ports, set to <2>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - #interrupt-cells: specifies the number of cells needed to encode an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) interrupt source. The value must be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - compatible: Should contain "rockchip,rk3399-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - reg: Two register ranges as listed in the reg-names property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - reg-names: Must include the following names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - "axi-base"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - "apb-base"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clocks: Must contain an entry for each entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) See ../clocks/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clock-names: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - "aclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - "aclk-perf"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - "hclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - "pm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - msi-map: Maps a Requester ID to an MSI controller and associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) msi-specifier data. See ./pci-msi.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - interrupts: Three interrupt entries must be specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - interrupt-names: Must include the following names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - "sys"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - "legacy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - "client"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - resets: Must contain seven entries for each entry in reset-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) See ../reset/reset.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - reset-names: Must include the following names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - "core"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - "mgmt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - "mgmt-sticky"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - "pipe"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - "pm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - "aclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - "pclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - pinctrl-names : The pin control state names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - pinctrl-0: The "default" pinctrl state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - #interrupt-cells: specifies the number of cells needed to encode an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) interrupt source. The value must be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - interrupt-map-mask and interrupt-map: standard PCI properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Required properties for legacy PHY model (deprecated):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - phy-names: MUST be "pcie-phy".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Required properties for per-lane PHY model (preferred):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - phys: Must contain an phandle to a PHY for each entry in phy-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - phy-names: Must include 4 entries for all 4 lanes even if some of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) them won't be used for your cases. Entries are of the form "pcie-phy-N":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) where N ranges from 0 to 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) for changing the #phy-cells of phy node to support it)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Optional Property:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) - aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) using 24MHz OSC for RC's PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) - ep-gpios: contain the entry for pre-reset GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) - num-lanes: number of lanes to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) - vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) - vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *Interrupt controller child node*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) The core controller provides a single interrupt for legacy INTx. The PCIe node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) should contain an interrupt controller node as a target for the PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 'interrupt-map' property. This node represents the domain at which the four
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) INTx interrupts are decoded and routed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) Required properties for Interrupt controller child node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) - interrupt-controller: identifies the node as an interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) - #address-cells: specifies the number of cells needed to encode an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) address. The value must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) - #interrupt-cells: specifies the number of cells needed to encode an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) interrupt source. The value must be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pcie0: pcie@f8000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) compatible = "rockchip,rk3399-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) clock-names = "aclk", "aclk-perf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "hclk", "pm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) bus-range = <0x0 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) interrupt-names = "sys", "legacy", "client";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) assigned-clock-rates = <100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) num-lanes = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) msi-map = <0x0 &its 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) reg-names = "axi-base", "apb-base";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "pm", "pclk", "aclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* deprecated legacy PHY model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) phys = <&pcie_phy>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) phy-names = "pcie-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pinctrl-0 = <&pcie_clkreq>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) interrupt-map-mask = <0 0 0 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) interrupt-map = <0 0 0 1 &pcie0_intc 0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) <0 0 0 2 &pcie0_intc 1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) <0 0 0 3 &pcie0_intc 2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) <0 0 0 4 &pcie0_intc 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pcie0_intc: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pcie0: pcie@f8000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* preferred per-lane PHY model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags