Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Rockchip AXI PCIe Endpoint Controller DT description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: Should contain "rockchip,rk3399-pcie-ep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: Two register ranges as listed in the reg-names property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg-names: Must include the following names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	- "apb-base"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	- "mem-base"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - clocks: Must contain an entry for each entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 		See ../clocks/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - clock-names: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	- "aclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	- "aclk-perf"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	- "hclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	- "pm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - resets: Must contain seven entries for each entry in reset-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	   See ../reset/reset.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - reset-names: Must include the following names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	- "core"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	- "mgmt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	- "mgmt-sticky"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	- "pipe"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	- "pm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	- "aclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	- "pclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - pinctrl-names : The pin control state names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - pinctrl-0: The "default" pinctrl state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - phys: Must contain an phandle to a PHY for each entry in phy-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - phy-names: Must include 4 entries for all 4 lanes even if some of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   them won't be used for your cases. Entries are of the form "pcie-phy-N":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)   where N ranges from 0 to 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)   (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   for changing the #phy-cells of phy node to support it)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - rockchip,max-outbound-regions: Maximum number of outbound regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Optional Property:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - num-lanes: number of lanes to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - max-functions: Maximum number of functions that can be configured (default 1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) pcie0-ep: pcie@f8000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	compatible = "rockchip,rk3399-pcie-ep";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	#address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	rockchip,max-outbound-regions = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	clock-names = "aclk", "aclk-perf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		      "hclk", "pm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	max-functions = /bits/ 8 <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	num-lanes = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	reg-names = "apb-base", "mem-base";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		      "pm", "pclk", "aclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	pinctrl-0 = <&pcie_clkreq>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };