^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Renesas R-Car PCIe interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) compatible: "renesas,pcie-r8a7742" for the R8A7742 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) "renesas,pcie-r8a7743" for the R8A7743 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) "renesas,pcie-r8a7744" for the R8A7744 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) "renesas,pcie-r8a774a1" for the R8A774A1 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) "renesas,pcie-r8a774b1" for the R8A774B1 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "renesas,pcie-r8a774c0" for the R8A774C0 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) "renesas,pcie-r8a7779" for the R8A7779 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) "renesas,pcie-r8a7790" for the R8A7790 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "renesas,pcie-r8a7791" for the R8A7791 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "renesas,pcie-r8a7793" for the R8A7793 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "renesas,pcie-r8a7795" for the R8A7795 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "renesas,pcie-r8a7796" for the R8A77960 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "renesas,pcie-r8a77961" for the R8A77961 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "renesas,pcie-r8a77980" for the R8A77980 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) "renesas,pcie-r8a77990" for the R8A77990 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) RZ/G1 compatible device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) RZ/G2 compatible device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) When compatible with the generic version, nodes must list the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) SoC-specific version corresponding to the platform first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) followed by the generic version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - reg: base address and length of the PCIe controller registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - #address-cells: set to <3>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - #size-cells: set to <2>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - bus-range: PCI bus numbers covered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - device_type: set to "pci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - ranges: ranges for the PCI memory and I/O regions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - dma-ranges: ranges for the inbound memory regions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - interrupts: two interrupt sources for MSI interrupts, followed by interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) source for hardware related interrupts (e.g. link speed change).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - #interrupt-cells: set to <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - interrupt-map-mask and interrupt-map: standard PCI properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) to define the mapping of the PCIe interface to interrupt numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - clocks: from common clock binding: clock specifiers for the PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) and PCIe bus clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - clock-names: from common clock binding: should be "pcie" and "pcie_bus".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - phys: from common PHY binding: PHY phandle and specifier (only make sense
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - phy-names: from common PHY binding: should be "pcie".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SoC-specific DT Entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pcie: pcie@fe000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) reg = <0 0xfe000000 0 0x80000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) bus-range = <0x00 0xff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) interrupts = <0 116 4>, <0 117 4>, <0 118 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) interrupt-map-mask = <0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) interrupt-map = <0 0 0 0 &gic 0 116 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) clocks = <&mstp3_clks R8A7791_CLK_PCIE>, <&pcie_bus_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clock-names = "pcie", "pcie_bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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