Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) # Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) title: Renesas R-Car PCIe Endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)       - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)           - renesas,r8a774a1-pcie-ep     # RZ/G2M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)           - renesas,r8a774b1-pcie-ep     # RZ/G2N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)           - renesas,r8a774c0-pcie-ep     # RZ/G2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)           - renesas,r8a774e1-pcie-ep     # RZ/G2H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)       - const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)     maxItems: 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   reg-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)       - const: apb-base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)       - const: memory0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)       - const: memory1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)       - const: memory2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)       - const: memory3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)   power-domains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)   resets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)   clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)   clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)       - const: pcie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)   max-functions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)     minimum: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)     maximum: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)   - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)   - reg-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)   - resets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)   - power-domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)   - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)   - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)   - max-functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)     #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)     #include <dt-bindings/power/r8a774c0-sysc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)      pcie0_ep: pcie-ep@fe000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)             compatible = "renesas,r8a774c0-pcie-ep",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)                          "renesas,rcar-gen3-pcie-ep";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)             reg = <0xfe000000 0x80000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)                   <0xfe100000 0x100000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)                   <0xfe200000 0x200000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)                   <0x30000000 0x8000000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)                   <0x38000000 0x8000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)             reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)             resets = <&cpg 319>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)             power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)             clocks = <&cpg CPG_MOD 319>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)             clock-names = "pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)             max-functions = /bits/ 8 <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)     };