^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) PCI bus bridges have standardized Device Tree bindings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) PCI Bus Binding to: IEEE Std 1275-1994
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) And for the interrupt mapping part:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Open Firmware Recommended Practice: Interrupt Mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Additionally to the properties specified in the above standards a host bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) driver implementation may support the following properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - linux,pci-domain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) If present this property assigns a fixed PCI domain number to a host bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) otherwise an unstable (across boots) unique number will be assigned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) It is required to either not set this property at all or set it for all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) host bridges in the system, otherwise potentially conflicting domain numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) may be assigned to root buses behind different host bridges. The domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) number for each host bridge in the system must be unique.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - max-link-speed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) If present this property specifies PCI gen for link capability. Host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) drivers could add this as a strategy to avoid unnecessary operation for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsupported link speed, for instance, trying to do training for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) for gen2, and '1' for gen1. Any other values are invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - reset-gpios:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) If present this property specifies PERST# GPIO. Host drivers can parse the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) GPIO and apply fundamental reset to endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - supports-clkreq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) If present this property specifies that CLKREQ signal routing exists from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) root port to downstream device and host bridge drivers can do programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) which depends on CLKREQ signal existence. For example, programming root port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PCI-PCI Bridge properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) -------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PCIe root ports and switch ports may be described explicitly in the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) tree, as children of the host bridge node. Even though those devices are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) discoverable by probing, it might be necessary to describe properties that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) aren't provided by standard PCIe capabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) document, it is a five-cell address encoded as (phys.hi phys.mid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) phys.lo size.hi size.lo). phys.hi should contain the device's BDF as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) The bus number is defined by firmware, through the standard bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) configuration mechanism. If this port is a switch port, then firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) allocates the bus number and writes it into the Secondary Bus Number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) register of the bridge directly above this port. Otherwise, the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) number of a root port is the first number in the bus-range property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) defaulting to zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) If firmware leaves the ARI Forwarding Enable bit set in the bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) above this port, then phys.hi contains the 8-bit function number as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 0b00000000 bbbbbbbb ffffffff 00000000. Note that the PCIe specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) recommends that firmware only leaves ARI enabled when it knows that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) OS is ARI-aware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) - external-facing:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) When present, the port is external-facing. All bridges and endpoints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) downstream of this port are external to the machine. The OS can, for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) example, use this information to identify devices that cannot be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) trusted with relaxed DMA protection, as users could easily attach
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) malicious devices to this port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pcie@10000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) compatible = "pci-host-ecam-generic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pcie@0008 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Root port 00:01.0 is external-facing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) reg = <0x00000800 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) external-facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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