^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Renesas AHB to PCI bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) -------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) This is the bridge used internally to connect the USB controllers to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) AHB. There is one bridge instance per USB port connected to the internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) OHCI and EHCI controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - compatible: "renesas,pci-r8a7742" for the R8A7742 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) "renesas,pci-r8a7743" for the R8A7743 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) "renesas,pci-r8a7744" for the R8A7744 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "renesas,pci-r8a7745" for the R8A7745 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "renesas,pci-r8a7790" for the R8A7790 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "renesas,pci-r8a7791" for the R8A7791 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "renesas,pci-r8a7793" for the R8A7793 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "renesas,pci-r8a7794" for the R8A7794 SoC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "renesas,pci-rcar-gen2" for a generic R-Car Gen2 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) RZ/G1 compatible device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) When compatible with the generic version, nodes must list the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) SoC-specific version corresponding to the platform first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) followed by the generic version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - reg: A list of physical regions to access the device: the first is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) the operational registers for the OHCI/EHCI controllers and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) second is for the bridge configuration and control registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - interrupts: interrupt for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - clocks: The reference to the device clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - bus-range: The PCI bus number range; as this is a single bus, the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) should be specified as the same value twice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - #address-cells: must be 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - #size-cells: must be 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - #interrupt-cells: must be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - interrupt-map: standard property used to define the mapping of the PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) interrupts to the GIC interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - interrupt-map-mask: standard property that helps to define the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - dma-ranges: a single range for the inbound memory region. If not supplied,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) allowed combinations of address and size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Example SoC configuration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) pci0: pci@ee090000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) reg = <0x0 0xee090000 0x0 0xc00>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) <0x0 0xee080000 0x0 0x1100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bus-range = <0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) interrupt-map-mask = <0xff00 0 0 0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) usb@1,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) reg = <0x800 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) phys = <&usb0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) phy-names = "usb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) usb@2,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) reg = <0x1000 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) phys = <&usb0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) phy-names = "usb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) Example board setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) &pci0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) pinctrl-0 = <&usb0_pins>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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