^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) TI Keystone PCIe interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Keystone PCI host Controller is based on the Synopsys DesignWare PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) hardware version 3.65. It shares common functions with the PCIe DesignWare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) core driver and inherits common properties defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Documentation/devicetree/bindings/pci/designware-pcie.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) for the details of DesignWare DT bindings. Additional properties are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) described here as well as properties that are not applicable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Required Properties:-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Should be "ti,am654-pcie-rc" for RC on AM654x SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) reg: Three register ranges as listed in the reg-names property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) TI specific application registers, "config" for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) configuration space address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) interrupt-cells: should be set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) (required if the compatible is "ti,keystone-pcie")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) (required if the compatible is "ti,am654-pcie-rc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ti,syscon-pcie-id : phandle to the device control module required to set device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) id and vendor id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ti,syscon-pcie-mode : phandle to the device control module required to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PCI in either RC mode or EP mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) pcie_msi_intc: msi-interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) interrupt-parent = <&gic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) pcie_intc: Interrupt controller device node for Legacy IRQ chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) interrupt-cells: should be set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) pcie_intc: legacy-interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) interrupt-parent = <&gic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) Optional properties:-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) phys: phandle to generic Keystone SerDes PHY for PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) phy-names: name of the generic Keystone SerDes PHY for PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) - If boot loader already does PCI link establishment, then phys and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) phy-names shouldn't be present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) interrupts: platform interrupt for error interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DesignWare DT Properties not applicable for Keystone PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) AM654 PCIe Endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ===================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) Required Properties:-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) compatibility: Should be "ti,am654-pcie-ep" for EP on AM654x SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) reg: Four register ranges as listed in the reg-names property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) TI specific application registers, "atu" for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) Address Translation Unit configuration registers and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "addr_space" used to map remote RC address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) num-ib-windows: As specified in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) Documentation/devicetree/bindings/pci/designware-pcie.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) num-ob-windows: As specified in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) Documentation/devicetree/bindings/pci/designware-pcie.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) num-lanes: As specified in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) Documentation/devicetree/bindings/pci/designware-pcie.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) power-domains: As documented by the generic PM domain bindings in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) Documentation/devicetree/bindings/power/power_domain.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ti,syscon-pcie-mode: phandle to the device control module required to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PCI in either RC mode or EP mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) Optional properties:-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) phys: list of PHY specifiers (used by generic PHY framework)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) phy-names: must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) number of lanes as specified in *num-lanes* property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ("phys" and "phy-names" DT bindings are specified in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) Documentation/devicetree/bindings/phy/phy-bindings.txt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) interrupts: platform interrupt for error interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pcie-ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) compatible = "ti,am654-pcie-ep";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) reg = <0x5500000 0x1000>, <0x5501000 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) <0x10000000 0x8000000>, <0x5506000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) reg-names = "app", "dbics", "addr_space", "atu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) power-domains = <&k3_pds 120>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ti,syscon-pcie-mode = <&pcie0_mode>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) num-lanes = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) num-ib-windows = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) num-ob-windows = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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