^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) This document describes the generic device tree binding for describing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) relationship between PCI(e) devices and IOMMU(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Each PCI(e) device under a root complex is uniquely identified by its Requester
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) ID (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Function number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) For the purpose of this document, when treated as a numeric value, a RID is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) formatted such that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Bits [15:8] are the Bus number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Bits [7:3] are the Device number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Bits [2:0] are the Function number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Any other bits required for padding must be zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) IOMMUs may distinguish PCI devices through sideband data derived from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Requester ID. While a given PCI device can only master through one IOMMU, a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) bus).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) The generic 'iommus' property is insufficient to describe this relationship,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) and a mechanism is required to map from a PCI device to its IOMMU and sideband
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) For generic IOMMU bindings, see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Documentation/devicetree/bindings/iommu/iommu.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PCI root complex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Optional properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) The property is an arbitrary number of tuples of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) (rid-base,iommu,iommu-base,length).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Any RID r in the interval [rid-base, rid-base + length) is associated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - iommu-map-mask: A mask to be applied to each Requester ID prior to being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) mapped to an IOMMU specifier per the iommu-map property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) Example (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ===========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) iommu: iommu@a {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) reg = <0xa 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) compatible = "vendor,some-iommu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #iommu-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pci: pci@f {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) reg = <0xf 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) compatible = "vendor,pcie-root-complex";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * The sideband data provided to the IOMMU is the RID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * identity-mapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) iommu-map = <0x0 &iommu 0x0 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) Example (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ===========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) iommu: iommu@a {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) reg = <0xa 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) compatible = "vendor,some-iommu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #iommu-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pci: pci@f {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) reg = <0xf 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) compatible = "vendor,pcie-root-complex";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * The sideband data provided to the IOMMU is the RID with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * function bits masked out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) iommu-map = <0x0 &iommu 0x0 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) iommu-map-mask = <0xfff8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) Example (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ===========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) iommu: iommu@a {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) reg = <0xa 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) compatible = "vendor,some-iommu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #iommu-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pci: pci@f {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) reg = <0xf 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) compatible = "vendor,pcie-root-complex";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * The sideband data provided to the IOMMU is the RID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * but the high bits of the bus number are flipped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) iommu-map = <0x0000 &iommu 0x8000 0x8000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) <0x8000 &iommu 0x0000 0x8000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) Example (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ===========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) iommu_a: iommu@a {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) reg = <0xa 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) compatible = "vendor,some-iommu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #iommu-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) iommu_b: iommu@b {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) reg = <0xb 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) compatible = "vendor,some-iommu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #iommu-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) iommu_c: iommu@c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) reg = <0xc 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) compatible = "vendor,some-iommu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #iommu-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pci: pci@f {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) reg = <0xf 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) compatible = "vendor,pcie-root-complex";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Devices with bus number 0-127 are mastered via IOMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * a, with sideband data being RID[14:0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Devices with bus number 128-255 are mastered via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * IOMMU b, with sideband data being RID[14:0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * No devices master via IOMMU c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) iommu-map = <0x0000 &iommu_a 0x0000 0x8000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) <0x8000 &iommu_b 0x0000 0x8000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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