Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Marvell Armada 7K/8K PCIe interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This PCIe host controller is based on the Synopsys DesignWare PCIe IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) and thus inherits all the common properties defined in designware-pcie.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - compatible: "marvell,armada8k-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reg: must contain two register regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)    - the control register region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)    - the config space region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - reg-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)    - "ctrl" for the control register region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)    - "config" for the config space region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - interrupts: Interrupt specifier for the PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clocks: reference to the PCIe controller clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - clock-names: mandatory if there is a second clock, in this case the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)    name must be "core" for the first clock and "reg" for the second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)    one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - phys: phandle(s) to PHY node(s) following the generic PHY bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	Either 1, 2 or 4 PHYs might be needed depending on the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	PCIe lanes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - phy-names: names of the PHYs corresponding to the number of lanes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	2 PHYs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	pcie@f2600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		reg-names = "ctrl", "config";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		#address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		bus-range = <0 0xff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		ranges = <0x81000000 0 0xf9000000 0  0xf9000000 0 0x10000	/* downstream I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 			  0x82000000 0 0xf6000000 0  0xf6000000 0 0xf00000>;	/* non-prefetchable memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		interrupt-map-mask = <0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		num-lanes = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		clocks = <&cpm_syscon0 1 13>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	};