^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Marvell EBU PCIe interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Mandatory properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - compatible: one of the following values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) marvell,armada-370-pcie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) marvell,armada-xp-pcie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) marvell,dove-pcie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) marvell,kirkwood-pcie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - #address-cells, set to <3>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - #size-cells, set to <2>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - #interrupt-cells, set to <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - bus-range: PCI bus numbers covered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - device_type, set to "pci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - ranges: ranges describing the MMIO registers to control the PCIe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) interfaces, and ranges describing the MBus windows needed to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) the memory and I/O regions of each PCIe interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - msi-parent: Link to the hardware entity that serves as the Message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Signaled Interrupt controller for this PCI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) The ranges describing the MMIO registers have the following layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) where:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * r is a 32-bits value that gives the offset of the MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) registers of this PCIe interface, from the base of the internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * s is a 32-bits value that give the size of this MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) registers area. This range entry translates the '0x82000000 0 r' PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) of the internal register window (as identified by MBUS_ID(0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 0x01)).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) The ranges describing the MBus windows have the following layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) where:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * t is the type of the MBus window (as defined by the standard PCI DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) bindings), 1 for I/O and 2 for memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * s is the PCI slot that corresponds to this PCIe interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * w is the 'target ID' value for the MBus window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * a the 'attribute' value for the MBus window.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Since the location and size of the different MBus windows is not fixed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) hardware, and only determined in runtime, those ranges cover the full first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 4 GB of the physical address space, and do not translate into a valid CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) In addition, the device tree node must have sub-nodes describing each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PCIe interface, having the following mandatory properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) - reg: used only for interrupt mapping, so only the first four bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) are used to refer to the correct bus number and device number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - assigned-addresses: reference to the MMIO registers used to control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) this PCIe interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) - clocks: the clock associated to this PCIe interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) - marvell,pcie-port: the physical PCIe port number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) - status: either "disabled" or "okay"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) - device_type, set to "pci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) - #address-cells, set to <3>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) - #size-cells, set to <2>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) - #interrupt-cells, set to <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) - ranges, translating the MBus windows ranges of the parent node into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) standard PCI addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) - interrupt-map-mask and interrupt-map, standard PCI properties to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) define the mapping of the PCIe interface to interrupt numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) and the following optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) - marvell,pcie-lane: the physical PCIe lane number, for ports having
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) multiple lanes. If this property is not found, we assume that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) value is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) - reset-gpios: optional GPIO to PERST#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) - reset-delay-us: delay in us to wait after reset de-assertion, if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) specified will default to 100ms, as required by the PCIe specification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pcie-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) compatible = "marvell,armada-xp-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bus-range = <0x00 0xff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) msi-parent = <&mpic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ranges =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pcie@1,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) reg = <0x0800 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0x81000000 0 0 0x81000000 0x1 0 1 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) interrupt-map-mask = <0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) interrupt-map = <0 0 0 0 &mpic 58>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) marvell,pcie-port = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) marvell,pcie-lane = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* low-active PERST# reset on GPIO 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) reset-gpios = <&gpio0 25 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* wait 20ms for device settle after reset deassertion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) reset-delay-us = <20000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) clocks = <&gateclk 5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pcie@2,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) reg = <0x1000 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0x81000000 0 0 0x81000000 0x2 0 1 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) interrupt-map-mask = <0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) interrupt-map = <0 0 0 0 &mpic 59>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) marvell,pcie-port = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) marvell,pcie-lane = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clocks = <&gateclk 6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pcie@3,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) reg = <0x1800 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 0x81000000 0 0 0x81000000 0x3 0 1 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) interrupt-map-mask = <0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) interrupt-map = <0 0 0 0 &mpic 60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) marvell,pcie-port = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) marvell,pcie-lane = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) clocks = <&gateclk 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pcie@4,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) reg = <0x2000 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 0x81000000 0 0 0x81000000 0x4 0 1 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) interrupt-map-mask = <0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) interrupt-map = <0 0 0 0 &mpic 61>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) marvell,pcie-port = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) marvell,pcie-lane = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) clocks = <&gateclk 8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pcie@5,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) reg = <0x2800 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 0x81000000 0 0 0x81000000 0x5 0 1 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) interrupt-map-mask = <0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) interrupt-map = <0 0 0 0 &mpic 62>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) marvell,pcie-port = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) marvell,pcie-lane = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) clocks = <&gateclk 9>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pcie@6,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) reg = <0x3000 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 0x81000000 0 0 0x81000000 0x6 0 1 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) interrupt-map-mask = <0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) interrupt-map = <0 0 0 0 &mpic 63>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) marvell,pcie-port = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) marvell,pcie-lane = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) clocks = <&gateclk 10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pcie@7,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) reg = <0x3800 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 0x81000000 0 0 0x81000000 0x7 0 1 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) interrupt-map-mask = <0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) interrupt-map = <0 0 0 0 &mpic 64>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) marvell,pcie-port = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) marvell,pcie-lane = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) clocks = <&gateclk 11>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pcie@8,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) reg = <0x4000 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 0x81000000 0 0 0x81000000 0x8 0 1 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) interrupt-map-mask = <0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) interrupt-map = <0 0 0 0 &mpic 65>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) marvell,pcie-port = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) marvell,pcie-lane = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) clocks = <&gateclk 12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pcie@9,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) reg = <0x4800 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 0x81000000 0 0 0x81000000 0x9 0 1 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) interrupt-map-mask = <0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) interrupt-map = <0 0 0 0 &mpic 99>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) marvell,pcie-port = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) marvell,pcie-lane = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) clocks = <&gateclk 26>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pcie@a,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) reg = <0x5000 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 0x81000000 0 0 0x81000000 0xa 0 1 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) interrupt-map-mask = <0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) interrupt-map = <0 0 0 0 &mpic 103>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) marvell,pcie-port = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) marvell,pcie-lane = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) clocks = <&gateclk 27>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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