Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Mobiveil AXI PCIe Root Port Bridge DT description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) has up to 8 outbound and inbound windows for the address translation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - #address-cells: Address representation for root ports, set to <3>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - #size-cells: Size representation for root ports, set to <2>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - #interrupt-cells: specifies the number of cells needed to encode an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	interrupt source. The value must be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - compatible: Should contain "mbvl,gpex40-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - reg: Should contain PCIe registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	Mandatory:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	"config_axi_slave": PCIe controller registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	"csr_axi_slave"	  : Bridge config registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	Optional:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	"gpio_slave"	  : GPIO registers to control slot power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	"apb_csr"	  : MSI registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - device_type: must be "pci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - apio-wins : number of requested apio outbound windows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		default 2 outbound windows are configured -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		1. Config window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		2. Memory window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - ppio-wins : number of requested ppio inbound windows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		default 1 inbound memory window is configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - bus-range: PCI bus numbers covered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - interrupt-controller: identifies the node as an interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - #interrupt-cells: specifies the number of cells needed to encode an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	interrupt source. The value must be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - interrupts: The interrupt line of the PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		last cell of this field is set to 4 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		denote it as IRQ_TYPE_LEVEL_HIGH type interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - interrupt-map-mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	interrupt-map: standard PCI properties to define the mapping of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	PCI interface to interrupt numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - ranges: ranges for the PCI memory regions (I/O space region is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	supported by hardware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	Please refer to the standard PCI bus binding document for a more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	detailed explanation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ++++++++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	pcie0: pcie@a0000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		#address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		compatible = "mbvl,gpex40-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		reg =	<0xa0000000 0x00001000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			<0xb0000000 0x00010000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			<0xff000000 0x00200000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			<0xb0010000 0x00001000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		reg-names =	"config_axi_slave",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 				"csr_axi_slave",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 				"gpio_slave",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 				"apb_csr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		apio-wins = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		ppio-wins = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		bus-range = <0x00000000 0x000000ff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		interrupt-parent = <&gic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		interrupts = < 0 89 4 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		interrupt-map-mask = <0 0 0 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		interrupt-map = <0 0 0 0 &pci_express 0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 				<0 0 0 1 &pci_express 1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 				<0 0 0 2 &pci_express 2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 				<0 0 0 3 &pci_express 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	};