^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) MediaTek Gen2 PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: Should contain one of the following strings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) "mediatek,mt2701-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) "mediatek,mt2712-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) "mediatek,mt7622-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) "mediatek,mt7623-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "mediatek,mt7629-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - device_type: Must be "pci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - reg: Base addresses and lengths of the PCIe subsys and root ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - reg-names: Names of the above areas to use during resource lookup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - #address-cells: Address representation for root ports (must be 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - #size-cells: Size representation for root ports (must be 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clocks: Must contain an entry for each entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) See ../clocks/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Mandatory entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - sys_ckN :transaction layer and data link layer clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Required entries for MT2701/MT7623:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - free_ck :for reference clock of PCIe subsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Required entries for MT2712/MT7622:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - ahb_ckN :AHB slave interface operating clock for CSR access and RC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) initiated MMIO access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Required entries for MT7622:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - axi_ckN :application layer MMIO channel operating clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) pcie_mac_ck/pcie_pipe_ck is turned off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - obff_ckN :OBFF functional block operating clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - pipe_ckN :LTSSM and PHY/MAC layer operating clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) where N starting from 0 to one less than the number of root ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - phys: List of PHY specifiers (used by generic PHY framework).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) number of PHYs as specified in *phys* property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - power-domains: A phandle and power domain specifier pair to the power domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) which is responsible for collapsing and restoring power to the peripheral.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - bus-range: Range of bus numbers associated with this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - ranges: Ranges for the PCI memory and I/O regions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Required properties for MT7623/MT2701:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - #interrupt-cells: Size representation for interrupts (must be 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Please refer to the standard PCI bus binding document for a more detailed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) explanation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - resets: Must contain an entry for each entry in reset-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) See ../reset/reset.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) number of root ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Required properties for MT2712/MT7622:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) -interrupts: A list of interrupt outputs of the controller, must have one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) entry for each PCIe port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) In addition, the device tree node must have sub-nodes describing each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PCIe port interface, having the following mandatory properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) - device_type: Must be "pci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) - reg: Only the first four bytes are used to refer to the correct bus number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) and device number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - #address-cells: Must be 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - #size-cells: Must be 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) - #interrupt-cells: Must be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) Please refer to the standard PCI bus binding document for a more detailed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) explanation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) - ranges: Sub-ranges distributed from the PCIe controller node. An empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) property is sufficient.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) Examples for MT7623:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) hifsys: syscon@1a000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) compatible = "mediatek,mt7623-hifsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "mediatek,mt2701-hifsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) reg = <0 0x1a000000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #reset-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pcie: pcie@1a140000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) compatible = "mediatek,mt7623-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) <0 0x1a142000 0 0x1000>, /* Port0 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) <0 0x1a143000 0 0x1000>, /* Port1 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) <0 0x1a144000 0 0x1000>; /* Port2 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) reg-names = "subsys", "port0", "port1", "port2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) interrupt-map-mask = <0xf800 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) <&hifsys CLK_HIFSYS_PCIE0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) <&hifsys CLK_HIFSYS_PCIE1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) <&hifsys CLK_HIFSYS_PCIE2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) <&hifsys MT2701_HIFSYS_PCIE1_RST>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) <&hifsys MT2701_HIFSYS_PCIE2_RST>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) <&pcie2_phy PHY_TYPE_PCIE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bus-range = <0x00 0xff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pcie@0,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reg = <0x0000 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) interrupt-map-mask = <0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pcie@1,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) reg = <0x0800 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) interrupt-map-mask = <0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pcie@2,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) reg = <0x1000 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) interrupt-map-mask = <0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) Examples for MT2712:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pcie: pcie@11700000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) compatible = "mediatek,mt2712-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) reg = <0 0x11700000 0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) <0 0x112ff000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) reg-names = "port0", "port1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) <&pericfg CLK_PERI_PCIE0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) <&pericfg CLK_PERI_PCIE1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) phy-names = "pcie-phy0", "pcie-phy1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) bus-range = <0x00 0xff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pcie0: pcie@0,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) reg = <0x0000 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) interrupt-map-mask = <0 0 0 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) interrupt-map = <0 0 0 1 &pcie_intc0 0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) <0 0 0 2 &pcie_intc0 1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) <0 0 0 3 &pcie_intc0 2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) <0 0 0 4 &pcie_intc0 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pcie_intc0: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pcie1: pcie@1,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) reg = <0x0800 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) interrupt-map-mask = <0 0 0 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) interrupt-map = <0 0 0 1 &pcie_intc1 0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) <0 0 0 2 &pcie_intc1 1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) <0 0 0 3 &pcie_intc1 2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) <0 0 0 4 &pcie_intc1 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pcie_intc1: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) Examples for MT7622:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pcie: pcie@1a140000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) compatible = "mediatek,mt7622-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) reg = <0 0x1a140000 0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) <0 0x1a143000 0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) <0 0x1a145000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) reg-names = "subsys", "port0", "port1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) <&pciesys CLK_PCIE_P1_MAC_EN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) <&pciesys CLK_PCIE_P0_AHB_EN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) <&pciesys CLK_PCIE_P1_AHB_EN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) <&pciesys CLK_PCIE_P0_AUX_EN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) <&pciesys CLK_PCIE_P1_AUX_EN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) <&pciesys CLK_PCIE_P0_AXI_EN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) <&pciesys CLK_PCIE_P1_AXI_EN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) <&pciesys CLK_PCIE_P0_OBFF_EN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) <&pciesys CLK_PCIE_P1_OBFF_EN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) <&pciesys CLK_PCIE_P0_PIPE_EN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) <&pciesys CLK_PCIE_P1_PIPE_EN>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) phy-names = "pcie-phy0", "pcie-phy1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) bus-range = <0x00 0xff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pcie0: pcie@0,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) reg = <0x0000 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) interrupt-map-mask = <0 0 0 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) interrupt-map = <0 0 0 1 &pcie_intc0 0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) <0 0 0 2 &pcie_intc0 1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) <0 0 0 3 &pcie_intc0 2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) <0 0 0 4 &pcie_intc0 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pcie_intc0: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pcie1: pcie@1,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) reg = <0x0800 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) interrupt-map-mask = <0 0 0 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) interrupt-map = <0 0 0 1 &pcie_intc1 0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) <0 0 0 2 &pcie_intc1 1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) <0 0 0 3 &pcie_intc1 2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) <0 0 0 4 &pcie_intc1 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pcie_intc1: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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