Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) NXP Layerscape PCIe Gen4 controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) the common properties defined in mobiveil-pcie.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - compatible: should contain the platform identifier such as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)   "fsl,lx2160a-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg: base addresses and lengths of the PCIe controller register blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   "csr_axi_slave": Bridge config registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   "config_axi_slave": PCIe controller registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - interrupts: A list of interrupt outputs of the controller. Must contain an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   entry for each entry in the interrupt-names property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - interrupt-names: It could include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   "intr": The interrupt that is asserted for controller interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   "aer": Asserted for aer interrupt when chip support the aer interrupt with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   "pme": Asserted for pme interrupt when chip support the pme interrupt with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - dma-coherent: Indicates that the hardware IP block can ensure the coherency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   of the data transferred from/to the IP block. This can avoid the software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)   cache flush/invalid actions, and improve the performance significantly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - msi-parent : See the generic MSI binding described in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   Documentation/devicetree/bindings/interrupt-controller/msi.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	pcie@3400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		compatible = "fsl,lx2160a-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		       0x80 0x00000000 0x0 0x00001000>; /* configuration space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		reg-names = "csr_axi_slave", "config_axi_slave";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		interrupt-names = "aer", "pme", "intr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		#address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		apio-wins = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		ppio-wins = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		bus-range = <0x0 0xff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		msi-parent = <&its>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		interrupt-map-mask = <0 0 0 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 				<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 				<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 				<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	};