Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Freescale Layerscape PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This PCIe host controller is based on the Synopsys DesignWare PCIe IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) and thus inherits all the common properties defined in designware-pcie.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) This controller derives its clocks from the Reset Configuration Word (RCW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) which is used to describe the PLL settings at the time of chip-reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Also as per the available Reference Manuals, there is no specific 'version'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) register available in the Freescale PCIe controller register set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) which can allow determining the underlying DesignWare PCIe controller version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - compatible: should contain the platform identifier such as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   RC mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)         "fsl,ls1021a-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)         "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)         "fsl,ls2088a-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)         "fsl,ls1088a-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)         "fsl,ls1046a-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)         "fsl,ls1043a-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)         "fsl,ls1012a-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)         "fsl,ls1028a-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)   EP mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	"fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	"fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - reg: base addresses and lengths of the PCIe controller register blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - interrupts: A list of interrupt outputs of the controller. Must contain an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)   entry for each entry in the interrupt-names property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - interrupt-names: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   "intr": The interrupt that is asserted for controller interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - fsl,pcie-scfg: Must include two entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)   The first entry must be a link to the SCFG device node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)   The second entry must be '0' or '1' based on physical PCIe controller index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)   This is used to get SCFG PEXN registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - dma-coherent: Indicates that the hardware IP block can ensure the coherency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)   of the data transferred from/to the IP block. This can avoid the software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)   cache flush/invalid actions, and improve the performance significantly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	pcie@3400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		compatible = "fsl,ls1021a-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		reg-names = "regs", "config";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		interrupt-names = "intr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		fsl,pcie-scfg = <&scfg 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		#address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		num-lanes = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		bus-range = <0x0 0xff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 			  0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000   /* prefetchable memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		interrupt-map-mask = <0 0 0 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 				<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 				<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 				<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	};