Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) HiSilicon Kirin SoCs PCIe host DT description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) It shares common functions with the PCIe DesignWare core driver and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) inherits common properties defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Documentation/devicetree/bindings/pci/designware-pcie.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) Additional properties are described here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Required properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	"hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - reg: Should contain rc_dbi, apb, phy, config registers location and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - reg-names: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   "dbi": controller configuration registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   "apb": apb Ctrl register defined by Kirin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   "phy": apb PHY register defined by Kirin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   "config": PCIe configuration space registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Example based on kirin960:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	pcie@f4000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		compatible = "hisilicon,kirin-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		      <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		reg-names = "dbi","apb","phy", "config";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		bus-range = <0x0  0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		#address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		num-lanes = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		interrupt-map-mask = <0xf800 0 0 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		interrupt-map = <0x0 0 0 1 &gic 0 0 0  282 4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 				<0x0 0 0 2 &gic 0 0 0  283 4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 				<0x0 0 0 3 &gic 0 0 0  284 4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 				<0x0 0 0 4 &gic 0 0 0  285 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		clock-names = "pcie_phy_ref", "pcie_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			      "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		reset-gpios = <&gpio11 1 0 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	};