^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) title: Generic PCI host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - Will Deacon <will@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Firmware-initialised PCI host controllers and PCI emulations, such as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) virtio-pci implementations found in kvmtool and other para-virtualised
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) systems, do not require driver support for complexities such as regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) and clock management. In fact, the controller may not even require the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) configuration of a control interface by the operating system, instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) presenting a set of fixed windows describing a subset of IO, Memory and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Configuration Spaces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Configuration Space is assumed to be memory-mapped (as opposed to being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) accessed via an ioport) and laid out with a direct correspondence to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) geography of a PCI bus address by concatenating the various components to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) form an offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) For CAM, this 24-bit offset is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) cfg_offset(bus, device, function, register) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) bus << 16 | device << 11 | function << 8 | register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) While ECAM extends this by 4 bits to accommodate 4k of function space:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) cfg_offset(bus, device, function, register) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) bus << 20 | device << 15 | function << 12 | register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) description: Depends on the layout of configuration space (CAM vs ECAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) respectively). May also have more specific compatibles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PCIe host controller in Arm Juno based on PLDA XpressRICH3-AXI IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - const: arm,juno-r1-pcie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - const: plda,xpressrich3-axi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - const: pci-host-ecam-generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ThunderX PCI host controller for pass-1.x silicon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Firmware-initialized PCI host controller to on-chip devices found on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) some Cavium ThunderX processors. These devices have ECAM-based config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) access, but the BARs are all at fixed addresses. We handle the fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) addresses by synthesizing Enhanced Allocation (EA) capabilities for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) these devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) const: cavium,pci-host-thunder-ecam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) - description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Cavium ThunderX PEM firmware-initialized PCIe host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const: cavium,pci-host-thunder-pem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) - description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) HiSilicon Hip06/Hip07 PCIe host bridge in almost-ECAM mode. Some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) firmware places the host controller in a mode where it is ECAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) compliant for all devices other than the root complex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) - hisilicon,hip06-pcie-ecam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) - hisilicon,hip07-pcie-ecam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) - description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) In some cases, firmware may already have configured the Synopsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DesignWare PCIe controller in RC mode with static ATU window mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) that cover all config, MMIO and I/O spaces in a [mostly] ECAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) compatible fashion. In this case, there is no need for the OS to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) perform any low level setup of clocks, PHYs or device registers, nor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) is there any reason for the driver to reconfigure ATU windows for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) config and/or IO space accesses at runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) In cases where the IP was synthesized with a minimum ATU window size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) of 64 KB, it cannot be supported by the generic ECAM driver, because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) it requires special config space accessors that filter accesses to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) device #1 and beyond on the first bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) - marvell,armada8k-pcie-ecam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) - socionext,synquacer-pcie-ecam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) - const: snps,dw-pcie-ecam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) - description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) CAM or ECAM compliant PCI host controllers without any quirks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) - pci-host-cam-generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) - pci-host-ecam-generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) The Configuration Space base address and size, as accessed from the parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bus. The base address corresponds to the first bus in the "bus-range"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) property. If no "bus-range" is specified, this will be bus 0 (the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) default). Some host controllers have a 2nd non-compliant address range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) so 2 entries are allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) minItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) maxItems: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ranges:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) As described in IEEE Std 1275-1994, but must provide at least a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) definition of non-prefetchable memory. One or both of prefetchable Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) and IO Space may also be provided.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) minItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) maxItems: 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dma-coherent: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) - ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) allOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) - $ref: /schemas/pci/pci-bus.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) - if:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const: arm,juno-r1-pcie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) then:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) - dma-coherent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) - if:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) not:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) - cavium,pci-host-thunder-pem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) - hisilicon,hip06-pcie-ecam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) - hisilicon,hip07-pcie-ecam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) then:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unevaluatedProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) bus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pcie@40000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) compatible = "pci-host-cam-generic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) bus-range = <0x0 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) // CPU_PHYSICAL(2) SIZE(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) reg = <0x0 0x40000000 0x0 0x1000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) // BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #interrupt-cells = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) < 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) <0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) <0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) // PCI_DEVICE(3) INT#(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ...
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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