Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) HiSilicon Hip05 and Hip06 PCIe host bridge DT description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) It shares common functions with the PCIe DesignWare core driver and inherits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) common properties defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Documentation/devicetree/bindings/pci/designware-pcie.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) Additional properties are described here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Required properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - reg: Should contain rc_dbi, config registers location and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - reg-names: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   "rc_dbi": controller configuration registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   "config": PCIe configuration space registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - port-id: Should be 0, 1, 2 or 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - status: Either "ok" or "disabled".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - dma-coherent: Present if DMA operations are coherent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Hip05 Example (note that Hip06 is the same except compatible):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	pcie@b0080000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		reg-names = "rc_dbi", "config";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		bus-range = <0  15>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		msi-parent = <&its_pcie>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		#address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		num-lanes = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		port-id = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		interrupt-map-mask = <0xf800 0 0 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		interrupt-map = <0x0 0 0 1 &mbigen_pcie 1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 				 0x0 0 0 2 &mbigen_pcie 2 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 				 0x0 0 0 3 &mbigen_pcie 3 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 				 0x0 0 0 4 &mbigen_pcie 4 13>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	};