Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) HiSilicon STB PCIe host bridge DT description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) It shares common functions with the DesignWare PCIe core driver and inherits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) common properties defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Documentation/devicetree/bindings/pci/designware-pcie.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) Additional properties are described here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Required properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - compatible: Should be one of the following strings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 		"hisilicon,hi3798cv200-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - reg: Should contain sysctl, rc_dbi, config registers location and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - reg-names: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   "control": control registers of PCIe controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   "rc-dbi": configuration space of PCIe controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   "config": configuration transaction space of PCIe controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - bus-range: PCI bus numbers covered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - interrupts: MSI interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - interrupt-names: Must include "msi" entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - clocks: List of phandle and clock specifier pairs as listed in clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)   property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - clock-name: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   "aux": auxiliary gate clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)   "pipe": pipe gate clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   "sys": sys gate clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   "bus": bus gate clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - resets: List of phandle and reset specifier pairs as listed in reset-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - reset-names: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)   "soft": soft reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)   "sys": sys reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   "bus": bus reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - vpcie-supply: The regulator in charge of PCIe port power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - phys: List of phandle and phy mode specifier, should be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - phy-names: Must be "phy".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	pcie@f9860000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		compatible = "hisilicon,hi3798cv200-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		reg = <0xf9860000 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		      <0xf0000000 0x2000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		      <0xf2000000 0x01000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		reg-names = "control", "rc-dbi", "config";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		#address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		bus-range = <0 15>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		num-lanes = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		ranges=<0x81000000 0 0 0xf4000000 0 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		interrupt-names = "msi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		interrupt-map-mask = <0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		clocks = <&crg PCIE_AUX_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 			 <&crg PCIE_PIPE_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 			 <&crg PCIE_SYS_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 			 <&crg PCIE_BUS_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		clock-names = "aux", "pipe", "sys", "bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		reset-names = "soft", "sys", "bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		phys = <&combphy1 PHY_TYPE_PCIE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		phy-names = "phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	};