^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Altera PCIe MSI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: should contain "altr,msi-1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg: specifies the physical base address of the controller and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) the length of the memory mapped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - reg-names: must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) "csr": CSR registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "vector_slave": vectors slave port region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - interrupts: specifies the interrupt source of the parent interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) controller. The format of the interrupt specifier depends on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) parent interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - num-vectors: number of vectors, range 1 to 32.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - msi-controller: indicates that this is MSI controller node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) msi0: msi@0xFF200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) compatible = "altr,msi-1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) reg = <0xFF200000 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 0xFF200010 0x00000080>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) reg-names = "csr", "vector_slave";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) interrupt-parent = <&hps_0_arm_gic_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) interrupts = <0 42 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) msi-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) num-vectors = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };