Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Aardvark PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) The Device Tree node describing an Aardvark PCIe controller must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) contain the following properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  - compatible: Should be "marvell,armada-3700-pcie"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  - reg: range of registers for the PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  - interrupts: the interrupt line of the PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  - #address-cells: set to <3>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  - #size-cells: set to <2>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  - device_type: set to "pci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  - ranges: ranges for the PCI memory and I/O regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  - #interrupt-cells: set to <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  - msi-controller: indicates that the PCIe controller can itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)    handle MSI interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  - msi-parent: pointer to the MSI controller to be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  - interrupt-map-mask and interrupt-map: standard PCI properties to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)    define the mapping of the PCIe interface to interrupt numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  - bus-range: PCI bus numbers covered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  - phys: the PCIe PHY handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  - max-link-speed: see pci.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  - reset-gpios: see pci.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) In addition, the Device Tree describing an Aardvark PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) must include a sub-node that describes the legacy interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) built into the PCIe controller. This sub-node must have the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  - interrupt-controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  - #interrupt-cells: set to <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	pcie0: pcie@d0070000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		compatible = "marvell,armada-3700-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		reg = <0 0xd0070000 0 0x20000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		#address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		bus-range = <0x00 0xff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		msi-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		msi-parent = <&pcie0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		ranges = <0x82000000 0 0xe8000000   0 0xe8000000 0 0x1000000 /* Port 0 MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			  0x81000000 0 0xe9000000   0 0xe9000000 0 0x10000>; /* Port 0 IO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		interrupt-map-mask = <0 0 0 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		interrupt-map = <0 0 0 1 &pcie_intc 0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 				<0 0 0 2 &pcie_intc 1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 				<0 0 0 3 &pcie_intc 2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 				<0 0 0 4 &pcie_intc 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		phys = <&comphy1 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		pcie_intc: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 			interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 			#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	};