Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Freescale 83xx and 512x PCI bridges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Freescale 83xx and 512x SOCs include the same PCI bridge core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 83xx/512x specific notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg: should contain two address length tuples
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)     The first is for the internal PCI bridge registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)     The second is for the PCI config space access registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Example (MPC8313ERDB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	pci0: pci@e0008500 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 		interrupt-map = <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 				/* IDSEL 0x0E -mini PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 				 0x7000 0x0 0x0 0x1 &ipic 18 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 				 0x7000 0x0 0x0 0x2 &ipic 18 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 				 0x7000 0x0 0x0 0x3 &ipic 18 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 				 0x7000 0x0 0x0 0x4 &ipic 18 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 				/* IDSEL 0x0F - PCI slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 				 0x7800 0x0 0x0 0x1 &ipic 17 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 				 0x7800 0x0 0x0 0x2 &ipic 18 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 				 0x7800 0x0 0x0 0x3 &ipic 17 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 				 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		interrupt-parent = <&ipic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		interrupts = <66 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		bus-range = <0x0 0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 			  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		clock-frequency = <66666666>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		#address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		reg = <0xe0008500 0x100		/* internal registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		       0xe0008300 0x8>;		/* config space access registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		compatible = "fsl,mpc8349-pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	};