Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Texas Instruments OMAP compatible OPP supply description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) OMAP5, DRA7, and AM57 family of SoCs have Class0 AVS eFuse registers which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) contain data that can be used to adjust voltages programmed for some of their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) supplies for more efficient operation. This binding provides the information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) needed to read these values and use them to program the main regulator during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) an OPP transitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Also, some supplies may have an associated vbb-supply which is an Adaptive Body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Bias regulator which much be transitioned in a specific sequence with regards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) to the vdd-supply and clk when making an OPP transition. By supplying two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) regulators to the device that will undergo OPP transitions we can make use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) of the multi regulator binding that is part of the OPP core described here [1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) to describe both regulators needed by the platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) [1] Documentation/devicetree/bindings/opp/opp.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Required Properties for Device Node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - vdd-supply: phandle to regulator controlling VDD supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - vbb-supply: phandle to regulator controlling Body Bias supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	      (Usually Adaptive Body Bias regulator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Required Properties for opp-supply node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - compatible: Should be one of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	"ti,omap-opp-supply" - basic OPP supply controlling VDD and VBB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	"ti,omap5-opp-supply" - OMAP5+ optimized voltages in efuse(class0)VDD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 			    along with VBB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	"ti,omap5-core-opp-supply" - OMAP5+ optimized voltages in efuse(class0) VDD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 			    but no VBB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - reg: Address and length of the efuse register set for the device (mandatory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	only for "ti,omap5-opp-supply")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - ti,efuse-settings: An array of u32 tuple items providing information about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	optimized efuse configuration. Each item consists of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	volt: voltage in uV - reference voltage (OPP voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	efuse_offseet: efuse offset from reg where the optimized voltage is stored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - ti,absolute-max-voltage-uv: absolute maximum voltage for the OPP supply.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Device Node (CPU)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	cpu0: cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		vdd-supply = <&vcc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		vbb-supply = <&abb_mpu>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* OMAP OPP Supply with Class0 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) opp_supply_mpu: opp_supply@4a003b20 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	compatible = "ti,omap5-opp-supply";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	reg = <0x4a003b20 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	ti,efuse-settings = <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	/* uV   offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	1060000 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	1160000 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	1210000 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	ti,absolute-max-voltage-uv = <1500000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };