^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ===================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) the CPU frequencies subset and voltage value of each OPP varies based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) the silicon variant in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Qualcomm Technologies, Inc. Process Voltage Scaling Tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) defines the voltage and frequency value based on the msm-id in SMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) and speedbin blown in the efuse combination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) to provide the OPP framework with required information (existing HW bitmap).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) This is used to determine the voltage and frequency value for each OPP of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) operating-points-v2 table when it is parsed by the OPP framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) In 'cpu' nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - operating-points-v2: Phandle to the operating-points-v2 table to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) In 'operating-points-v2' table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - compatible: Should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) apq8064, ipq8064, msm8960 and ipq8074.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) In 'cpu' nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - power-domains: A phandle pointing to the PM domain specifier which provides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) the performance states available for active state management.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Please refer to the power-domains bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Documentation/devicetree/bindings/power/power_domain.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) and also examples below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - power-domain-names: Should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - 'cpr' for qcs404.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) In 'operating-points-v2' table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) efuse registers that has information about the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) speedbin that is used to select the right frequency/voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) value pair.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Please refer the for nvmem-cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) and also examples below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) In every OPP node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Bitmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 0: MSM8996 V3, speedbin 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 1: MSM8996 V3, speedbin 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 2: MSM8996 V3, speedbin 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 3: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 4: MSM8996 SG, speedbin 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 5: MSM8996 SG, speedbin 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 6: MSM8996 SG, speedbin 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 7-31: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Example 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) CPU0: cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) compatible = "qcom,kryo";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) reg = <0x0 0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) clocks = <&kryocc 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) cpu-supply = <&pm8994_s11_saw>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) operating-points-v2 = <&cluster0_opp>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #cooling-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) next-level-cache = <&L2_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) L2_0: l2-cache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) compatible = "cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) cache-level = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) CPU1: cpu@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) compatible = "qcom,kryo";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) reg = <0x0 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) clocks = <&kryocc 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) cpu-supply = <&pm8994_s11_saw>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) operating-points-v2 = <&cluster0_opp>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #cooling-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) next-level-cache = <&L2_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) CPU2: cpu@100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) compatible = "qcom,kryo";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) reg = <0x0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) clocks = <&kryocc 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) cpu-supply = <&pm8994_s11_saw>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) operating-points-v2 = <&cluster1_opp>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #cooling-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) next-level-cache = <&L2_1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) L2_1: l2-cache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) compatible = "cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) cache-level = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) CPU3: cpu@101 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) compatible = "qcom,kryo";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) reg = <0x0 0x101>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) clocks = <&kryocc 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) cpu-supply = <&pm8994_s11_saw>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) operating-points-v2 = <&cluster1_opp>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #cooling-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) next-level-cache = <&L2_1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) cpu-map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) cluster0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) core0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) cpu = <&CPU0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) core1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) cpu = <&CPU1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) cluster1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) core0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) cpu = <&CPU2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) core1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) cpu = <&CPU3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) cluster0_opp: opp_table0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) compatible = "operating-points-v2-kryo-cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) nvmem-cells = <&speedbin_efuse>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) opp-307200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) opp-hz = /bits/ 64 <307200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) opp-supported-hw = <0x77>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) opp-384000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) opp-hz = /bits/ 64 <384000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) opp-422400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) opp-hz = /bits/ 64 <422400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) opp-460800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) opp-hz = /bits/ 64 <460800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) opp-480000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) opp-hz = /bits/ 64 <480000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) opp-537600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) opp-hz = /bits/ 64 <537600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) opp-556800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) opp-hz = /bits/ 64 <556800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) opp-614400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) opp-hz = /bits/ 64 <614400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) opp-652800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) opp-hz = /bits/ 64 <652800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) opp-691200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) opp-hz = /bits/ 64 <691200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) opp-729600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) opp-hz = /bits/ 64 <729600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) opp-768000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) opp-hz = /bits/ 64 <768000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) opp-844800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) opp-hz = /bits/ 64 <844800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) opp-supported-hw = <0x77>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) opp-902400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) opp-hz = /bits/ 64 <902400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) opp-960000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) opp-hz = /bits/ 64 <960000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) opp-979200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) opp-hz = /bits/ 64 <979200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) opp-1036800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) opp-hz = /bits/ 64 <1036800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) opp-1056000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) opp-hz = /bits/ 64 <1056000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) opp-1113600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) opp-hz = /bits/ 64 <1113600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) opp-1132800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) opp-hz = /bits/ 64 <1132800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) opp-1190400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) opp-hz = /bits/ 64 <1190400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) opp-1209600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) opp-hz = /bits/ 64 <1209600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) opp-1228800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) opp-hz = /bits/ 64 <1228800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) opp-1286400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) opp-hz = /bits/ 64 <1286400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) opp-1324800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) opp-hz = /bits/ 64 <1324800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) opp-supported-hw = <0x5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) opp-1363200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) opp-hz = /bits/ 64 <1363200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) opp-supported-hw = <0x72>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) opp-1401600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) opp-hz = /bits/ 64 <1401600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) opp-supported-hw = <0x5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) opp-1440000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) opp-hz = /bits/ 64 <1440000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) opp-1478400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) opp-hz = /bits/ 64 <1478400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) opp-supported-hw = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) opp-1497600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) opp-hz = /bits/ 64 <1497600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) opp-supported-hw = <0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) opp-1516800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) opp-hz = /bits/ 64 <1516800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) opp-1593600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) opp-hz = /bits/ 64 <1593600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) opp-supported-hw = <0x71>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) opp-1996800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) opp-hz = /bits/ 64 <1996800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) opp-supported-hw = <0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) opp-2188800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) opp-hz = /bits/ 64 <2188800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) opp-supported-hw = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) cluster1_opp: opp_table1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) compatible = "operating-points-v2-kryo-cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) nvmem-cells = <&speedbin_efuse>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) opp-307200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) opp-hz = /bits/ 64 <307200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) opp-supported-hw = <0x77>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) opp-384000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) opp-hz = /bits/ 64 <384000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) opp-403200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) opp-hz = /bits/ 64 <403200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) opp-460800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) opp-hz = /bits/ 64 <460800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) opp-480000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) opp-hz = /bits/ 64 <480000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) opp-537600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) opp-hz = /bits/ 64 <537600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) opp-556800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) opp-hz = /bits/ 64 <556800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) opp-614400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) opp-hz = /bits/ 64 <614400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) opp-652800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) opp-hz = /bits/ 64 <652800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) opp-691200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) opp-hz = /bits/ 64 <691200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) opp-729600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) opp-hz = /bits/ 64 <729600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) opp-748800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) opp-hz = /bits/ 64 <748800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) opp-806400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) opp-hz = /bits/ 64 <806400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) opp-825600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) opp-hz = /bits/ 64 <825600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) opp-883200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) opp-hz = /bits/ 64 <883200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) opp-902400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) opp-hz = /bits/ 64 <902400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) opp-940800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) opp-hz = /bits/ 64 <940800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) opp-979200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) opp-hz = /bits/ 64 <979200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) opp-1036800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) opp-hz = /bits/ 64 <1036800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) opp-1056000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) opp-hz = /bits/ 64 <1056000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) opp-1113600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) opp-hz = /bits/ 64 <1113600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) opp-1132800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) opp-hz = /bits/ 64 <1132800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) opp-1190400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) opp-hz = /bits/ 64 <1190400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) opp-1209600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) opp-hz = /bits/ 64 <1209600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) opp-1248000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) opp-hz = /bits/ 64 <1248000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) opp-1286400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) opp-hz = /bits/ 64 <1286400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) opp-microvolt = <905000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) opp-1324800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) opp-hz = /bits/ 64 <1324800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) opp-1363200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) opp-hz = /bits/ 64 <1363200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) opp-1401600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) opp-hz = /bits/ 64 <1401600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) opp-1440000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) opp-hz = /bits/ 64 <1440000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) opp-1478400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) opp-hz = /bits/ 64 <1478400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) opp-1516800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) opp-hz = /bits/ 64 <1516800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) opp-1555200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) opp-hz = /bits/ 64 <1555200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) opp-1593600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) opp-hz = /bits/ 64 <1593600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) opp-1632000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) opp-hz = /bits/ 64 <1632000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) opp-1670400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) opp-hz = /bits/ 64 <1670400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) opp-1708800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) opp-hz = /bits/ 64 <1708800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) opp-1747200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) opp-hz = /bits/ 64 <1747200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) opp-supported-hw = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) opp-1785600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) opp-hz = /bits/ 64 <1785600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) opp-supported-hw = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) opp-1804800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) opp-hz = /bits/ 64 <1804800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) opp-supported-hw = <0x6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) opp-1824000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) opp-hz = /bits/ 64 <1824000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) opp-supported-hw = <0x71>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) opp-1900800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) opp-hz = /bits/ 64 <1900800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) opp-supported-hw = <0x74>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) opp-1920000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) opp-hz = /bits/ 64 <1920000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) opp-supported-hw = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) opp-1977600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) opp-hz = /bits/ 64 <1977600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) opp-supported-hw = <0x30>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) opp-1996800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) opp-hz = /bits/ 64 <1996800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) opp-supported-hw = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) opp-2054400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) opp-hz = /bits/ 64 <2054400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) opp-supported-hw = <0x30>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) opp-2073600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) opp-hz = /bits/ 64 <2073600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) opp-supported-hw = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) opp-2150400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) opp-hz = /bits/ 64 <2150400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) opp-supported-hw = <0x31>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) opp-2246400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) opp-hz = /bits/ 64 <2246400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) opp-supported-hw = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) opp-2342400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) opp-hz = /bits/ 64 <2342400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) opp-microvolt = <1140000 905000 1140000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) opp-supported-hw = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) clock-latency-ns = <200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) reserved-memory {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) smem_mem: smem-mem@86000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) reg = <0x0 0x86000000 0x0 0x200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) no-map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) smem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) compatible = "qcom,smem";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) memory-region = <&smem_mem>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) hwlocks = <&tcsr_mutex 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) qfprom: qfprom@74000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) compatible = "qcom,qfprom";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) reg = <0x00074000 0x8ff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) speedbin_efuse: speedbin@133 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) reg = <0x133 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) bits = <5 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) Example 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) CPU0: cpu@100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) compatible = "arm,cortex-a53";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) reg = <0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) clocks = <&apcs_glb>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) operating-points-v2 = <&cpu_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) power-domains = <&cpr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) power-domain-names = "cpr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) CPU1: cpu@101 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) compatible = "arm,cortex-a53";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) reg = <0x101>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) clocks = <&apcs_glb>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) operating-points-v2 = <&cpu_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) power-domains = <&cpr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) power-domain-names = "cpr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) CPU2: cpu@102 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) compatible = "arm,cortex-a53";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) reg = <0x102>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) clocks = <&apcs_glb>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) operating-points-v2 = <&cpu_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) power-domains = <&cpr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) power-domain-names = "cpr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) CPU3: cpu@103 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) compatible = "arm,cortex-a53";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) reg = <0x103>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) clocks = <&apcs_glb>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) operating-points-v2 = <&cpu_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) power-domains = <&cpr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) power-domain-names = "cpr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) cpu_opp_table: cpu-opp-table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) compatible = "operating-points-v2-kryo-cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) opp-1094400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) opp-hz = /bits/ 64 <1094400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) required-opps = <&cpr_opp1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) opp-1248000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) opp-hz = /bits/ 64 <1248000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) required-opps = <&cpr_opp2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) opp-1401600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) opp-hz = /bits/ 64 <1401600000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) required-opps = <&cpr_opp3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) cpr_opp_table: cpr-opp-table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) compatible = "operating-points-v2-qcom-level";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) cpr_opp1: opp1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) opp-level = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) qcom,opp-fuse-level = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) cpr_opp2: opp2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) opp-level = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) qcom,opp-fuse-level = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) cpr_opp3: opp3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) opp-level = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) qcom,opp-fuse-level = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) cpr: power-controller@b018000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) compatible = "qcom,qcs404-cpr", "qcom,cpr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) reg = <0x0b018000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) vdd-apc-supply = <&pms405_s3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #power-domain-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) operating-points-v2 = <&cpr_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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