^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Generic OPP (Operating Performance Points) Bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Devices work at voltage-current-frequency combinations and some implementations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) have the liberty of choosing these. These combinations are called Operating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Performance Points aka OPPs. This document defines bindings for these OPPs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) applicable across wide range of devices. For illustration purpose, this document
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) uses CPU as a device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) This document contain multiple versions of OPP binding and only one of them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) should be used per device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Binding 1: operating-points
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) This binding only supports voltage-frequency pairs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - operating-points: An array of 2-tuples items, and each item consists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) of frequency and voltage like <freq-kHz vol-uV>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) freq: clock frequency in kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) vol: voltage in microvolt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) compatible = "arm,cortex-a9";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) next-level-cache = <&L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) operating-points = <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* kHz uV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 792000 1100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 396000 950000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 198000 850000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Binding 2: operating-points-v2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Property: operating-points-v2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Devices supporting OPPs must set their "operating-points-v2" property with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) phandle to a OPP table in their DT node. The OPP core will use this phandle to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) find the operating points for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) This can contain more than one phandle for power domain providers that provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) multiple power domains. That is, one phandle for each power domain. If only one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) phandle is available, then the same OPP table will be used for all power domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) provided by the power domain provider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) If required, this can be extended for SoC vendor specific bindings. Such bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) should be documented as Documentation/devicetree/bindings/power/<vendor>-opp.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) and should have a compatible description like: "operating-points-v2-<vendor>".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * OPP Table Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) This describes the OPPs belonging to a device. This node can have following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) - compatible: Allow OPPs to express their compatibility. It should be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "operating-points-v2".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) - OPP nodes: One or more OPP nodes describing voltage-current-frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) combinations. Their name isn't significant but their phandle can be used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) reference an OPP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) - opp-shared: Indicates that device nodes using this OPP Table Node's phandle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) switch their DVFS state together, i.e. they share clock/voltage/current lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) Missing property means devices have independent clock/voltage/current lines,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) but they share OPP tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) - status: Marks the OPP table enabled/disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * OPP Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) This defines voltage-current-frequency combinations along with other related
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) - opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer. This is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) required property for all device nodes, unless another "required" property to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) uniquely identify the OPP nodes exists. Devices like power domains must have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) another (implementation dependent) property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) - opp-peak-kBps: Peak bandwidth in kilobytes per second, expressed as an array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) of 32-bit big-endian integers. Each element of the array represents the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) peak bandwidth value of each interconnect path. The number of elements should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) match the number of interconnect paths.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) - opp-microvolt: voltage in micro Volts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) A single regulator's voltage is specified with an array of size one or three.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) Single entry is for target voltage and three entries are for <target min max>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) voltages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) Entries for multiple regulators shall be provided in the same field separated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) by angular brackets <>. The OPP binding doesn't provide any provisions to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) relate the values to their power supplies or the order in which the supplies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) need to be configured and that is left for the implementation specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) Entries for all regulators shall be of the same size, i.e. either all use a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) single value or triplets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) - opp-microvolt-<name>: Named opp-microvolt property. This is exactly similar to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) the above opp-microvolt property, but allows multiple voltage ranges to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) provided for the same OPP. At runtime, the platform can pick a <name> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) matching opp-microvolt-<name> property will be enabled for all OPPs. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) platform doesn't pick a specific <name> or the <name> doesn't match with any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) opp-microvolt-<name> properties, then opp-microvolt property shall be used, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) - opp-microamp: The maximum current drawn by the device in microamperes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) considering system specific parameters (such as transients, process, aging,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) maximum operating temperature range etc.) as necessary. This may be used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) set the most efficient regulator operating mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) Should only be set if opp-microvolt is set for the OPP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) Entries for multiple regulators shall be provided in the same field separated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) by angular brackets <>. If current values aren't required for a regulator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) then it shall be filled with 0. If current values aren't required for any of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) the regulators, then this field is not required. The OPP binding doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) provide any provisions to relate the values to their power supplies or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) order in which the supplies need to be configured and that is left for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) implementation specific binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) - opp-microamp-<name>: Named opp-microamp property. Similar to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) opp-microvolt-<name> property, but for microamp instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) - opp-level: A value representing the performance level of the device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) expressed as a 32-bit integer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) - opp-avg-kBps: Average bandwidth in kilobytes per second, expressed as an array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) of 32-bit big-endian integers. Each element of the array represents the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) average bandwidth value of each interconnect path. The number of elements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) should match the number of interconnect paths. This property is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) meaningful in OPP tables where opp-peak-kBps is present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) - clock-latency-ns: Specifies the maximum possible transition latency (in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) nanoseconds) for switching to this OPP from any other OPP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) - turbo-mode: Marks the OPP to be used only for turbo modes. Turbo mode is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) available on some platforms, where the device can run over its operating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) frequency for a short duration of time limited by the device's power, current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) and thermal limits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) - opp-suspend: Marks the OPP to be used during device suspend. If multiple OPPs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) in the table have this, the OPP with highest opp-hz will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) - opp-supported-hw: This property allows a platform to enable only a subset of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) the OPPs from the larger set present in the OPP table, based on the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) version of the hardware (already known to the operating system).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) Each block present in the array of blocks in this property, represents a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) sub-group of hardware versions supported by the OPP. i.e. <sub-group A>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) <sub-group B>, etc. The OPP will be enabled if _any_ of these sub-groups match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) the hardware's version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) Each sub-group is a platform defined array representing the hierarchy of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) hardware versions supported by the platform. For a platform with three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) hierarchical levels of version (X.Y.Z), this field shall look like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) opp-supported-hw = <X1 Y1 Z1>, <X2 Y2 Z2>, <X3 Y3 Z3>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) Each level (eg. X1) in version hierarchy is represented by a 32 bit value, one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) bit per version and so there can be maximum 32 versions per level. Logical AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) (&) operation is performed for each level with the hardware's level version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) and a non-zero output for _all_ the levels in a sub-group means the OPP is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) supported by hardware. A value of 0xFFFFFFFF for each level in the sub-group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) will enable the OPP for all versions for the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) - status: Marks the node enabled/disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) - required-opps: This contains phandle to an OPP node in another device's OPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) table. It may contain an array of phandles, where each phandle points to an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) OPP of a different device. It should not contain multiple phandles to the OPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) nodes in the same OPP table. This specifies the minimum required OPP of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) device(s), whose OPP's phandle is present in this property, for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) functioning of the current device at the current OPP (where this property is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) present).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) compatible = "arm,cortex-a9";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) next-level-cache = <&L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) clocks = <&clk_controller 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clock-names = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) cpu-supply = <&cpu_supply0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) operating-points-v2 = <&cpu0_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) cpu@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) compatible = "arm,cortex-a9";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) next-level-cache = <&L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clocks = <&clk_controller 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) clock-names = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) cpu-supply = <&cpu_supply0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) operating-points-v2 = <&cpu0_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) cpu0_opp_table: opp_table0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) compatible = "operating-points-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) opp-1000000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) opp-hz = /bits/ 64 <1000000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) opp-microvolt = <975000 970000 985000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) opp-microamp = <70000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) clock-latency-ns = <300000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) opp-suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) opp-1100000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) opp-hz = /bits/ 64 <1100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) opp-microvolt = <1000000 980000 1010000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) opp-microamp = <80000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) clock-latency-ns = <310000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) opp-1200000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) opp-hz = /bits/ 64 <1200000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) opp-microvolt = <1025000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) clock-latency-ns = <290000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) turbo-mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) Example 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) independently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) compatible = "qcom,krait";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) next-level-cache = <&L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) clocks = <&clk_controller 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) clock-names = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) cpu-supply = <&cpu_supply0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) operating-points-v2 = <&cpu_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) cpu@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) compatible = "qcom,krait";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) next-level-cache = <&L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) clocks = <&clk_controller 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) clock-names = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) cpu-supply = <&cpu_supply1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) operating-points-v2 = <&cpu_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) cpu@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) compatible = "qcom,krait";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) reg = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) next-level-cache = <&L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) clocks = <&clk_controller 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) clock-names = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) cpu-supply = <&cpu_supply2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) operating-points-v2 = <&cpu_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) cpu@3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) compatible = "qcom,krait";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) reg = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) next-level-cache = <&L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) clocks = <&clk_controller 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) clock-names = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) cpu-supply = <&cpu_supply3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) operating-points-v2 = <&cpu_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) cpu_opp_table: opp_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) compatible = "operating-points-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Missing opp-shared property means CPUs switch DVFS states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * independently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) opp-1000000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) opp-hz = /bits/ 64 <1000000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) opp-microvolt = <975000 970000 985000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) opp-microamp = <70000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) clock-latency-ns = <300000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) opp-suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) opp-1100000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) opp-hz = /bits/ 64 <1100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) opp-microvolt = <1000000 980000 1010000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) opp-microamp = <80000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) clock-latency-ns = <310000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) opp-1200000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) opp-hz = /bits/ 64 <1200000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) opp-microvolt = <1025000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) opp-microamp = <90000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) lock-latency-ns = <290000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) turbo-mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) Example 3: Dual-cluster, Dual-core per cluster. CPUs within a cluster switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) DVFS state together.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) compatible = "arm,cortex-a7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) next-level-cache = <&L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) clocks = <&clk_controller 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) clock-names = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) cpu-supply = <&cpu_supply0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) operating-points-v2 = <&cluster0_opp>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) cpu@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) compatible = "arm,cortex-a7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) next-level-cache = <&L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) clocks = <&clk_controller 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) clock-names = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) cpu-supply = <&cpu_supply0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) operating-points-v2 = <&cluster0_opp>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) cpu@100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) compatible = "arm,cortex-a15";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) reg = <100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) next-level-cache = <&L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) clocks = <&clk_controller 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) clock-names = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) cpu-supply = <&cpu_supply1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) operating-points-v2 = <&cluster1_opp>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) cpu@101 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) compatible = "arm,cortex-a15";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) reg = <101>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) next-level-cache = <&L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) clocks = <&clk_controller 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) clock-names = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) cpu-supply = <&cpu_supply1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) operating-points-v2 = <&cluster1_opp>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) cluster0_opp: opp_table0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) compatible = "operating-points-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) opp-1000000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) opp-hz = /bits/ 64 <1000000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) opp-microvolt = <975000 970000 985000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) opp-microamp = <70000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) clock-latency-ns = <300000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) opp-suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) opp-1100000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) opp-hz = /bits/ 64 <1100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) opp-microvolt = <1000000 980000 1010000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) opp-microamp = <80000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) clock-latency-ns = <310000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) opp-1200000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) opp-hz = /bits/ 64 <1200000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) opp-microvolt = <1025000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) opp-microamp = <90000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) clock-latency-ns = <290000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) turbo-mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) cluster1_opp: opp_table1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) compatible = "operating-points-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) opp-1300000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) opp-hz = /bits/ 64 <1300000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) opp-microvolt = <1050000 1045000 1055000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) opp-microamp = <95000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) clock-latency-ns = <400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) opp-suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) opp-1400000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) opp-hz = /bits/ 64 <1400000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) opp-microvolt = <1075000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) opp-microamp = <100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) clock-latency-ns = <400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) opp-1500000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) opp-hz = /bits/ 64 <1500000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) opp-microvolt = <1100000 1010000 1110000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) opp-microamp = <95000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) clock-latency-ns = <400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) turbo-mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) Example 4: Handling multiple regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) compatible = "vendor,cpu-type";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) vcc0-supply = <&cpu_supply0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) vcc1-supply = <&cpu_supply1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) vcc2-supply = <&cpu_supply2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) operating-points-v2 = <&cpu0_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) cpu0_opp_table: opp_table0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) compatible = "operating-points-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) opp-1000000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) opp-hz = /bits/ 64 <1000000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) opp-microvolt = <970000>, /* Supply 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) <960000>, /* Supply 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) <960000>; /* Supply 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) opp-microamp = <70000>, /* Supply 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) <70000>, /* Supply 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) <70000>; /* Supply 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) clock-latency-ns = <300000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* OR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) opp-1000000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) opp-hz = /bits/ 64 <1000000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) opp-microvolt = <975000 970000 985000>, /* Supply 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) <965000 960000 975000>, /* Supply 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) <965000 960000 975000>; /* Supply 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) opp-microamp = <70000>, /* Supply 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) <70000>, /* Supply 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) <70000>; /* Supply 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) clock-latency-ns = <300000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* OR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) opp-1000000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) opp-hz = /bits/ 64 <1000000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) opp-microvolt = <975000 970000 985000>, /* Supply 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) <965000 960000 975000>, /* Supply 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) <965000 960000 975000>; /* Supply 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) opp-microamp = <70000>, /* Supply 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) <0>, /* Supply 1 doesn't need this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) <70000>; /* Supply 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) clock-latency-ns = <300000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) Example 5: opp-supported-hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) (example: three level hierarchy of versions: cuts, substrate and process)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) compatible = "arm,cortex-a7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) cpu-supply = <&cpu_supply>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) operating-points-v2 = <&cpu0_opp_table_slow>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) opp_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) compatible = "operating-points-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) opp-600000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * Supports all substrate and process versions for 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * cuts, i.e. only first four cuts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) opp-supported-hw = <0xF 0xFFFFFFFF 0xFFFFFFFF>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) opp-hz = /bits/ 64 <600000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) opp-800000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * Supports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * - cuts: only one, 6th cut (represented by 6th bit).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * - substrate: supports 16 different substrate versions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * - process: supports 9 different process versions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) opp-supported-hw = <0x20 0xff0000ff 0x0000f4f0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) opp-hz = /bits/ 64 <800000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) opp-900000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * Supports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * - All cuts and substrate where process version is 0x2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * - All cuts and process where substrate version is 0x2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) opp-supported-hw = <0xFFFFFFFF 0xFFFFFFFF 0x02>, <0xFFFFFFFF 0x01 0xFFFFFFFF>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) opp-hz = /bits/ 64 <900000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) Example 6: opp-microvolt-<name>, opp-microamp-<name>:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) (example: device with two possible microvolt ranges: slow and fast)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) compatible = "arm,cortex-a7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) operating-points-v2 = <&cpu0_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) cpu0_opp_table: opp_table0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) compatible = "operating-points-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) opp-1000000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) opp-hz = /bits/ 64 <1000000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) opp-microvolt-slow = <915000 900000 925000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) opp-microvolt-fast = <975000 970000 985000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) opp-microamp-slow = <70000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) opp-microamp-fast = <71000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) opp-1200000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) opp-hz = /bits/ 64 <1200000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) opp-microvolt-slow = <915000 900000 925000>, /* Supply vcc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) <925000 910000 935000>; /* Supply vcc1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) opp-microvolt-fast = <975000 970000 985000>, /* Supply vcc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) <965000 960000 975000>; /* Supply vcc1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) opp-microamp = <70000>; /* Will be used for both slow/fast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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