Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) On-Chip OTP Memory for Freescale Vybrid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)   - "fsl,vf610-ocotp", "syscon" for VF5xx/VF6xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)   #address-cells : Should be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   #size-cells : Should be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)   reg : Address and length of OTP controller and fuse map registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   clocks : ipg clock we associate with the OCOTP peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Example for Vybrid VF5xx/VF6xx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	ocotp: ocotp@400a5000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		compatible = "fsl,vf610-ocotp", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		reg = <0x400a5000 0xCF0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		clocks = <&clks VF610_CLK_OCOTP>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	};