^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Rockchip internal OTP (One Time Programmable) memory device tree bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: Should be one of the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - "rockchip,px30-otp" - for PX30 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - "rockchip,rk3308-otp" - for RK3308 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - reg: Should contain the registers location and size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - clocks: Must contain an entry for each entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - clock-names: Should be "otp", "apb_pclk" and "phy".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - resets: Must contain an entry for each entry in reset-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) See ../../reset/reset.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - reset-names: Should be "phy".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) See nvmem.txt for more information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) otp: otp@ff290000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) compatible = "rockchip,px30-otp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) reg = <0x0 0xff290000 0x0 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) <&cru PCLK_OTP_PHY>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) clock-names = "otp", "apb_pclk", "phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };