Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Nios II Processor Binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This binding specifies what properties available in the device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) representation of a Nios II Processor Core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Users can use sopc2dts tool for generating device tree sources (dts) from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Qsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - compatible: Compatible property value should be "altr,nios2-1.0".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - reg: Contains CPU index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - interrupt-controller: Specifies that the node is an interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - #interrupt-cells: Specifies the number of cells needed to encode an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		interrupt source, should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - clock-frequency: Contains the clock frequency for CPU, in Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - dcache-line-size: Contains data cache line size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - icache-line-size: Contains instruction line size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - dcache-size: Contains data cache size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - icache-size: Contains instruction cache size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - altr,pid-num-bits: Specifies the number of bits to use to represent the process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		identifier (PID).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - altr,tlb-num-entries: Specifies the number of entries in the TLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - altr,tlb-ptr-sz: Specifies size of TLB pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - altr,has-mul: Specifies CPU hardware multipy support, should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - altr,has-mmu: Specifies CPU support MMU support, should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - altr,has-initda: Specifies CPU support initda instruction, should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - altr,reset-addr: Specifies CPU reset address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - altr,exception-addr: Specifies CPU exception address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - altr,has-div: Specifies CPU hardware divide support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - altr,implementation: Nios II core implementation, this should be "fast";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	compatible = "altr,nios2-1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	clock-frequency = <125000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	dcache-line-size = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	icache-line-size = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	dcache-size = <32768>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	icache-size = <32768>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	altr,implementation = "fast";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	altr,pid-num-bits = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	altr,tlb-num-ways = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	altr,tlb-num-entries = <128>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	altr,tlb-ptr-sz = <7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	altr,has-div = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	altr,has-mul = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	altr,reset-addr = <0xc2800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	altr,fast-tlb-miss-addr = <0xc7fff400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	altr,exception-addr = <0xd0000020>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	altr,has-initda = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	altr,has-mmu = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };