^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) # Copyright 2019 BayLibre, SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $id: "http://devicetree.org/schemas/net/stm32-dwmac.yaml#"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) $schema: "http://devicetree.org/meta-schemas/core.yaml#"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) title: STMicroelectronics STM32 / MCU DWMAC glue layer controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - Alexandre Torgue <alexandre.torgue@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - Christophe Roullier <christophe.roullier@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) This file documents platform glue layer for stmmac.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) # We need a select here so we don't match all nodes with 'snps,dwmac'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) select:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - st,stm32-dwmac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - st,stm32mp1-dwmac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) allOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - $ref: "snps,dwmac.yaml#"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - st,stm32mp1-dwmac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - const: snps,dwmac-4.20a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - st,stm32-dwmac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - const: snps,dwmac-4.10a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - st,stm32-dwmac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - const: snps,dwmac-3.50a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) minItems: 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) maxItems: 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) - description: GMAC main clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - description: MAC TX clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - description: MAC RX clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - description: For MPU family, used for power mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - description: For MPU family, used for PHY without quartz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) minItems: 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) maxItems: 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - stmmaceth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) - mac-clk-tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) - mac-clk-rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) - ethstp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) - eth-ck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) st,syscon:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) $ref: "/schemas/types.yaml#/definitions/phandle-array"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) Should be phandle/offset pair. The phandle to the syscon node which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) encompases the glue register, and the offset of the control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) st,eth-clk-sel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) st,eth-ref-clk-sel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) set this property in RMII mode when you have PHY without crystal 50MHz and want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) select RCC clock instead of ETH_REF_CLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) - st,syscon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unevaluatedProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #include <dt-bindings/clock/stm32mp1-clks.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #include <dt-bindings/reset/stm32mp1-resets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #include <dt-bindings/mfd/stm32h7-rcc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) //Example 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ethernet0: ethernet@5800a000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg = <0x5800a000 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) reg-names = "stmmaceth";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) interrupts = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) interrupt-names = "macirq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) clock-names = "stmmaceth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "mac-clk-tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "mac-clk-rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "ethstp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "eth-ck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) clocks = <&rcc ETHMAC>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) <&rcc ETHTX>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) <&rcc ETHRX>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) <&rcc ETHSTP>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) <&rcc ETHCK_K>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) st,syscon = <&syscfg 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) snps,pbl = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) snps,axi-config = <&stmmac_axi_config_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) snps,tso;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) phy-mode = "rgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) //Example 2 (MCU example)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ethernet1: ethernet@40028000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) reg = <0x40028000 0x8000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) reg-names = "stmmaceth";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) interrupts = <0 61 0>, <0 62 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) interrupt-names = "macirq", "eth_wake_irq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) st,syscon = <&syscfg 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) snps,pbl = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) snps,mixed-burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) phy-mode = "mii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) //Example 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ethernet2: ethernet@40027000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) reg = <0x40028000 0x8000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) reg-names = "stmmaceth";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) interrupts = <61>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) interrupt-names = "macirq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) st,syscon = <&syscfg 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) snps,pbl = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) phy-mode = "mii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags