Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) STMicroelectronics SoC DWMAC glue layer controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This file documents differences between the core properties in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Documentation/devicetree/bindings/net/stmmac.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) and what is needed on STi platforms to program the stmmac glue logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) The device node has following properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  - compatible	: Can be "st,stih415-dwmac", "st,stih416-dwmac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)    "st,stih407-dwmac", "st,stid127-dwmac".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)    encompases the glue register, and the offset of the control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)    register available on STiH407 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  - pinctrl-0: pin-control for all the MII mode supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  - resets : phandle pointing to the system reset controller with correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)    reset line index for ethernet reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)    MAC can generate it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  - st,tx-retime-src: This specifies which clk is wired up to the mac for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)    retimeing tx lines. This is totally board dependent and can take one of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)    posssible values from "txclk", "clk_125" or "clkgen".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)    If not passed, the internal clock will be used by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  - sti-ethclk: this is the phy clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  - sti-clkconf: this is an extra sysconfig register, available in new SoCs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)    to program the clk retiming.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)    STiH407.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ethernet0: dwmac@9630000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	device_type = "network";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	reg = <0x9630000 0x8000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	reg-names = "stmmaceth";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	st,syscon = <&syscfg_sbc_reg 0x80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	st,gmac_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	resets = <&softreset STIH407_ETH1_SOFTRESET>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	reset-names = "stmmaceth";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		     <GIC_SPI 99 IRQ_TYPE_NONE>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		     <GIC_SPI 100 IRQ_TYPE_NONE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	snps,pbl = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	snps,mixed-burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	pinctrl-0 = <&pinctrl_rgmii1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	clock-names = "stmmaceth", "sti-ethclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	clocks = <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		 <&CLK_S_C0_FLEXGEN CLK_ETH_PHY>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };