Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Altera SOCFPGA SoC DWMAC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This is a variant of the dwmac/stmmac driver an inherits all descriptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) present in Documentation/devicetree/bindings/net/stmmac.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) The device node has additional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  - compatible	: For Cyclone5/Arria5 SoCs it should contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 		  "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 		  "altr,socfpga-stmmac-a10-s10".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 		  Along with "snps,dwmac" and any applicable more detailed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 		  designware version numbers documented in stmmac.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  - altr,sysmgr-syscon : Should be the phandle to the system manager node that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)    encompasses the glue register, the register offset, and the register shift.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)    On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)    on the Arria10/Stratix10/Agilex platforms, the register shift represents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)    bit for each emac to enable/disable signals from the FPGA fabric to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)    EMAC modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)    for ptp ref clk. This affects all emacs as the clock is common.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		DWMAC controller is connected emac splitter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) phy-mode: The phy mode the ethernet operates in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) This device node has additional phandle dependency, the sgmii converter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  - compatible	: Should be altr,gmii-to-sgmii-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  - reg-names	: Should be "eth_tse_control_port"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) gmii_to_sgmii_converter: phy@100000240 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	compatible = "altr,gmii-to-sgmii-2.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	reg = <0x00000001 0x00000240 0x00000008>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		<0x00000001 0x00000200 0x00000040>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	reg-names = "eth_tse_control_port";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) gmac0: ethernet@ff700000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	altr,sysmgr-syscon = <&sysmgr 0x60 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	reg = <0xff700000 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	interrupts = <0 115 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	interrupt-names = "macirq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	clocks = <&emac_0_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	clock-names = "stmmaceth";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	phy-mode = "sgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };