^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Qualcomm Technologies EMAC Gigabit Ethernet Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This network controller consists of two devices: a MAC and an SGMII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) internal PHY. Each device is represented by a device tree node. A phandle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) connects the MAC node to its corresponding internal phy node. Another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) phandle points to the external PHY node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) MAC node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - compatible : Should be "qcom,fsm9900-emac".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - reg : Offset and length of the register regions for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - interrupts : Interrupt number used by this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - mac-address : The 6-byte MAC address. If present, it is the default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) MAC address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - internal-phy : phandle to the internal PHY node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - phy-handle : phandle the the external PHY node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Internal PHY node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - compatible : Should be "qcom,fsm9900-emac-sgmii" or "qcom,qdf2432-emac-sgmii".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - reg : Offset and length of the register region(s) for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - interrupts : Interrupt number used by this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) The external phy child node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - reg : The phy address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) FSM9900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) emac0: ethernet@feb20000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) compatible = "qcom,fsm9900-emac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) reg = <0xfeb20000 0x10000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) <0xfeb36000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) interrupts = <76>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) <&gcc 6>, <&gcc 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "mdio_clk", "tx_clk", "rx_clk", "sys_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) internal-phy = <&emac_sgmii>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) phy-handle = <&phy0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) phy0: ethernet-phy@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pinctrl-0 = <&mdio_pins_a>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) emac_sgmii: ethernet@feb38000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) compatible = "qcom,fsm9900-emac-sgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) reg = <0xfeb38000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) interrupts = <80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) tlmm: pinctrl@fd510000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) compatible = "qcom,fsm9900-pinctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mdio_pins_a: mdio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pins = "gpio123", "gpio124";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) function = "mdio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) QDF2432:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) emac0: ethernet@38800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) compatible = "qcom,fsm9900-emac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) reg = <0x0 0x38800000 0x0 0x10000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) <0x0 0x38816000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) interrupts = <0 256 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) <&gcc 6>, <&gcc 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "mdio_clk", "tx_clk", "rx_clk", "sys_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) internal-phy = <&emac_sgmii>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) phy-handle = <&phy0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) phy0: ethernet-phy@4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) emac_sgmii: ethernet@410400 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) compatible = "qcom,qdf2432-emac-sgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) reg = <0x0 0x00410400 0x0 0xc00>, /* Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) <0x0 0x00410000 0x0 0x400>; /* Per-lane digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) interrupts = <0 254 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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