Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * NI XGE Ethernet controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)               older device trees with DMA engines co-located in the address map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)               with the one reg entry to describe the whole device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - reg: Address and length of the register set for the device. It contains the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)        information of registers in the same order as described by reg-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg-names: Should contain the reg names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	"dma":  DMA engine control and status region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)         "ctrl": MDIO and PHY control and status region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - interrupts: Should contain tx and rx interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - interrupt-names: Should be "rx" and "tx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - phy-mode: See ethernet.txt file in the same directory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - nvmem-cells: Phandle of nvmem cell containing the MAC address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - nvmem-cell-names: Should be "address"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - mdio subnode to indicate presence of MDIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   Use instead of phy-handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - phy-handle: See ethernet.txt file in the same directory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Examples (10G generic PHY):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	nixge0: ethernet@40000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		compatible = "ni,xge-enet-3.00";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		reg = <0x40000000 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		       0x41002000 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		reg-names = "dma", "ctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		nvmem-cells = <&eth1_addr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		nvmem-cell-names = "address";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		interrupt-names = "rx", "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		interrupt-parent = <&intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		phy-mode = "xgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		phy-handle = <&ethernet_phy1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		mdio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 			ethernet_phy1: ethernet-phy@4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 				compatible = "ethernet-phy-ieee802.3-c45";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 				reg = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Examples (10G generic PHY, no MDIO):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	nixge0: ethernet@40000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		compatible = "ni,xge-enet-2.00";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		reg = <0x40000000 0x6000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		nvmem-cells = <&eth1_addr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		nvmem-cell-names = "address";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		interrupt-names = "rx", "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		interrupt-parent = <&intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		phy-mode = "xgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		phy-handle = <&ethernet_phy1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) Examples (1G generic fixed-link + MDIO):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	nixge0: ethernet@40000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		compatible = "ni,xge-enet-2.00";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		reg = <0x40000000 0x6000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		nvmem-cells = <&eth1_addr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 		nvmem-cell-names = "address";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 		interrupt-names = "rx", "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 		interrupt-parent = <&intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 		phy-mode = "xgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 		fixed-link {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 			speed = <1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 			pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 			link-gpios = <&gpio0 63 GPIO_ACTIVE_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 		mdio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 			ethernet_phy1: ethernet-phy@4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 				compatible = "ethernet-phy-ieee802.3-c22";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 				reg = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 	};